FEAL60852A-02
1
Semiconductor
ML60852A
9/39
2.2.3.
Reading received data in receive packet ready interrupt procedure
The following flow chart illustrates the data reception process from the point of view of the application
firmware controlling the ML60852A. The IN block signifies the entry point to an event driven software,
where a packet of data has been successfully received and stored in the FIFO of ML60852A. Hence,
ML60852A generates an interrupt cause. A typical interrupt service procedure is outlined in this
diagram. Note that the processing for the data stage of a Control Write transfer is also included below.
Given that a control transfer is a message pipe (structured transfer) it can be seen that the processing of
received data for this type of transfer is much more intricate than other types of transfers
.
No
Start
Data read
Reset receive packet
ready status
Status register for each
end point: D0
Yes
Decode device
request
Control write
transfer?
Set transmit packet
ready
No
Callback function
Disable receive packet
ready interrupt of end
point 0
Interrupt enable register 1:
D6
EP0 status register: D1
Yes
All data received?
End
Occur Interrupt
