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FEAL60852A-02

Semiconductor

ML60852A

5/39

1.3.2.

Example of connections between H8/3048 (Hitachi make) and ML60852A

Notes:

*1: 5 to 3.3 V
*2: Pull-up control is used in this connection.
*3: This circuit is bus-powered.

Figure 2 Example of connections between Hitachi’s 16-bit microcontroller

(DMA transfer in dual address mode) H8/3048 and ML60852A

D15 to D8

D7 to D0

A7 to A1

–CS0

–CS1

–RD

–HWR

–IRQ1

–RESO

–DREQ0

H8/3048

ALE/PUCTL

D+

AD7 to AD0

D–

XIN

D15 to D8

XOUT

A6 to A0

–CS DACK0/DACK1

–RD

ADSEL

–WR

TEST1/TEST2

–INTR

–RESET

–DREQ0

ML60852

USB
Connector

VBUS

D+
D–
GND

100 k

Ω

100 k

Ω

3.3 V

1.5 k

Ω

220 k

Ω

12 MHz

5 V

Содержание ML60852A

Страница 1: ...ML60852A Application Manual USB device controller Version 1 02 FEAL60852A 02 DATE OCT 9 2001 1...

Страница 2: ...ion Manual 1 INTRODUCTION 1 2 EXAMPLES OF USB TRANSFER PROCEDURE 6 3 EXTERNAL INTERFACE 19 4 INTERRUPTS 29 5 OTHER FUNCTIONS 33 6 HANDLING UNUSED PINS 35 7 DIFFERENCES IN PIN ASSIGNMENT BETWEEN ML6085...

Страница 3: ...pt procedure in Bulk Out Transfer 12 2 3 3 Packet ready interrupt procedure in Bulk In Transfer 13 2 4 Interrupt Transfer 14 2 4 1 Outline of interrupt transfer 14 2 5 Isochronous Transfer 15 2 5 1 Ou...

Страница 4: ...acket Ready 31 4 4 SOF 31 4 5 USB Bus Reset Assert 32 4 6 USB Bus Reset Deassert 32 4 7 Suspend State 322 4 8 Awake 322 5 OTHER FUNCTIONS 33 5 1 5EP Mode and 6EP Mode 33 5 2 System Reset 33 5 3 Self p...

Страница 5: ...SB1 1 Supports Full speed 12 Mbps Supports four data transfer types Control transfer bulk transfer interrupt transfer and isochronous transfer Five or six end points Built in FIFO for data storage The...

Страница 6: ...UT CS RD WR RESET 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 AD0 AD1 AD2 AD3 V CC GND AD4 AD5 AD6 AD7 DREQ0 INTR D15 D14 D13 D12 TEST2 DACK1 D11 D10 D9 D...

Страница 7: ...Negative logic Chip select signal input pin RD I Negative logic Read signal input pin WR I Negative logic Write signal input pin INTR O 1 Interrupt request signal output pin DREQ0 DREQ1 O 1 DMA Reques...

Страница 8: ...sed in this connection 4 This circuit is bus powered Figure 1 Example of connections between OKI s 16 bit microcontroller MSM66573 and ML60852A VDD P127 D7 to D0 A6 to A0 A15 to A8 RD WR EXTINT1 VSS M...

Страница 9: ...Figure 2 Example of connections between Hitachi s 16 bit microcontroller DMA transfer in dual address mode H8 3048 and ML60852A VDD D15 to D8 D7 to D0 A7 to A1 CS0 CS1 RD HWR IRQ1 RESO DREQ0 VSS H8 30...

Страница 10: ...ons of ML60852A Carry out the settings of the operating conditions of the ML60852A to suit the system after referring to Chapter 3 EXTERNAL INTERFACE 2 1 2 Settings based on standard request Eleven ty...

Страница 11: ...uring a control transfer are the following Table 1 Registers used in the setup stage Function Register name Bits Device request bRequest Setup D7 to D0 Device request wValue LSB Setup D7 to D0 Device...

Страница 12: ...ad Control Write or a Control transfer without a data stage Hence the transfer will be processed according to the Request Type Start Disable EP0 transmit receive interrupt Read request End point 0 sta...

Страница 13: ...service procedure is outlined in this diagram Note that the processing for the data stage of a Control Write transfer is also included below Given that a control transfer is a message pipe structured...

Страница 14: ...ure This is due to the fact that end point 0 transmission is done through a Control Read transfer which is a message pipe structured pipe and hence much more tedious than other types of transfers Star...

Страница 15: ...6EP mode of the ML60852A have the DMA transfer function In addition the FIFO of EP1 EP2 and EP4 and also EP5 when in 6EP mode have a 2 layer configuration and it is possible to increase the transfer...

Страница 16: ...f view of the application firmware controlling the ML60852A The IN block shown below denotes the entry point to an event driven application firmware where a receive interrupt cause has been generated...

Страница 17: ...tion firmware controller ML60852A The IN block shown below denotes the entry point to an event driven firmware where a Transmit Packet Ready interrupt cause has been generated and the firmware should...

Страница 18: ...gh EP4 when in EP5 mode or EP1 through EP5 when in EP6 mode can be used for interrupt transfer These end points can be allocated individually for both interrupt in and interrupt out The FIFO size for...

Страница 19: ...sfer For these end points the transfer direction can be individually specified The FIFO size of EP4 in 5EP mode is 512 bytes In 6EP mode the FIFO size of EP4 EP5 is 256 bytes EP4 used in isochronous t...

Страница 20: ...60852A As specified by USB standards a single packet of isochronous data may be received in each USB frame As a result the packet reception process is started with detection of a SOF PID on the USB bu...

Страница 21: ...n application firmware controlling ML60852A As shown below given that a single packet of isochronous data may be transmitted in each USB frame the transmission processing procedure starts with detecti...

Страница 22: ...ed bytes count register of the ML60852A stores the number of received bytes at that point Although the host does not make a re transmit request when a CRC error occurs in isochronous transfer a functi...

Страница 23: ...s is used The Separate method is used when ADSEL is L In this case address lines are connected to AD6 to AD0 and data lines are connected to AD7 to AD0 The Multiplex method is used when ADSEL is H In...

Страница 24: ...handshake is received from the host computer the ML60852A resets again the transmit packet ready bit to 0 and makes DREQ0 and DREQ1 active 3 2 2 2 During reception The ML60852A sets the receive packe...

Страница 25: ...ount data is made when it is necessary for the local MCU to know the number of data bytes in the received packet Set D2 of the registers DMA0CON and DMA1CON to 1 when wanting to insert the byte count...

Страница 26: ...MA transfer bulk in transfer there is no need to set the packet ready bit of each end point from the local MCU side When data with the maximum packet size is written in the FIFO by the DMA controller...

Страница 27: ...interrupts When the MCU processes interrupts by edge detection it is impossible to detect interrupts when there are multiple interrupt causes because the ML60852A continues to maintain INTR in the act...

Страница 28: ...o 0 To use the 6 MHz one set D6 to 1 When supplying an external clock instead of using the built in oscillator circuit 48 MHz can also be used in addition to 6 MHz and 12 MHz For use of an external cl...

Страница 29: ...esonator An example of configuration using a ceramic resonator is shown below Ceramic resonator CSTCR6M00G15 R0 of Murata MFG make built in capacitor type Rf 1 M Figure 3 Example of oscillator circuit...

Страница 30: ...unt 3 4 4 Stopping the oscillator circuit The ML60852A has a function that stops the oscillator circuit to enter the low power state If D1 of the SYSCON register at address 2Fh is set to 1 in advance...

Страница 31: ...hem as shown in the dotted line block in the above figure The pull up resistor on the D line should be connected on the USB connector side of the series resistor Rs It is recommended that the pulled u...

Страница 32: ...nfigure the system mentioned above by regulating VBUS to 3 3 V thereby directly pulling up the D line system stability is further improved if the local MCU monitors the VBUS state and controls pull up...

Страница 33: ...ng to the necessary interrupt to 1 it is possible to enable only the required interrupt Resetting the bit to 0 disables the corresponding interrupt The bits of the registers INTSTAT1 and INTSTAT2 will...

Страница 34: ...receive FIFO of the corresponding end point the ML60852A automatically sets to 1 the receive packet ready bit of the end point status register EPnSTAT corresponding to that end point At this time if...

Страница 35: ...ing transmit packet ready bit of the EPnSTAT bit D1 register and hence generate an interrupt cause This interrupt indicates that the device transmit FIFO is ready to be written to again This process c...

Страница 36: ...ster is reset to 0 and INTR becomes inactive With this interrupt the local MCU can recognize completion of bus reset See Section 7 1 7 3 Reset Signaling in the USB Standard Rev 1 1 for details of a bu...

Страница 37: ...powered The ML60852A supports both Self powered and Bus powered operation If the ML60852A is used in the Bus powered mode the low power mode should be selected during the suspend state If D1 of the S...

Страница 38: ...or 5 ms or more and then restarts oscillation and outputs the remote wakeup signal onto the USB bus If D4 of the SYSCON register is set to 1 when the idle condition has already lasted for more than 5...

Страница 39: ...ing condition Pull up control is not used during the Separate mode ALE PUCTL The handling of the pin in this case is as follows ALE PUCTL Left open 6 3 DMA Transfer Control Pins D15 to D8 DREQ0 DREQ1...

Страница 40: ...nused pins Pin name I O Condition in which the pins are not used Pin handling method A6 to A0 I When the Multiplex mode is used H or L ALE PUCTL I When the Separate mode is used and pull up control is...

Страница 41: ...6 XIN XIN 28 A4 A4 7 XOUT XOUT Crystal or ceramic resonator connection pin 29 A3 A3 8 CS CS Chip select 30 A2 A2 9 RD RD Read 31 A1 A1 10 WR WR Write 32 A0 A0 Address input 11 RESET RESET Reset 33 DAC...

Страница 42: ...A enable bit of the DMA1CON register to 0 7 3 ALE Pin ALE PUCTL Pin pin 23 For use in multiplexed mode ADSEL H no change is required To use the pull up control function in separate mode ADSEL L connec...

Страница 43: ...rd party s industrial and intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed b...

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