Octagon PC-510, Руководство пользователя

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11-4
EZ I/O PC-510 user’s manual
Port addressing
Ports A, B, C and the control register are addressable.
Table 11-4 EZ I/O port address
Port I/O address
A Base address
B Base a 1
C Base a 2
Control register Base a 3
Base I/O address
The base I/O address for EZ I/O 1 is 334h (default) and the base I/O
address for EZ I/O 2 is 330h (default) but can be changed through
OctaGlue PCS_2 to one of four addresses. Refer to the
Interrupt routing
section in the IRQ routing and opto IRQs chapter to change the base
address of the EZ I/O chip.
Based on the I/O range select A and B, you can determine the port
addresses for EZ I/O 1 and EZ I/O 2 by reading 0A9h bit 4 and 0A9h bit
5. Refer to Table 11-5.
Table 11-5 Reading EZ I/O 1 and EZ I/O 2 port addresses at I/O location 0A9h
I/O range
select A
(bit 5)
I/O range
select B
(bit 4)
EZ I/O 2
base
address
EZ I/O 1
base address
0 1 130-133h 134-138
0 0 150-153h 154-158
1 0 350-353h 354-358
1 1 330-333h* 334-338*
* = default settings
≡
Configuring and programming the EZ I/O ports
J15 and J16, the digital I/O connectors, each have an Octagon EZ I/O
digital chip associated with them. The EZ I/O chip has three ports with
eight parallel I/O lines (bits) per port. This port can use one of four base
I/O addresses. All lines can be individually programmed as all inputs,
all outputs or individually as inputs or outputs. You can alter which
bits are inputs or outputs by writing a control command to the control
register of the EZ I/O. When a line is configured as an output, it can
sink a maximum of 15 mA at 0.4V or can source 15 mA at 2.4V. On
powerup and software or hardware reset, all digital I/O lines at J15 and
J16 are reset as inputs.