NY6 User Manual
Ver 1.3 2019/03/28
30
Chapter 3. System Control
3.1 Introduction
The INTx registers are used to enable the interrupt entrance for base timer(BT), Timer Counter(TM), PH
Counter, SPI and Comparator application. The INTFx registers are for reading flag originated from those
interrupt sources and written 0 to reset its flag individually. The BTF register is used to read BT signal of
different interval 0.256ms, 0.512ms, 1.024ms and 16.384ms. Moreover, the BTF is also memory lock
function for specific SRAM address 0x3E, 0x3F. The ONOFF register is to turn on block function such as
Timer Counter(TM), PH Counter (PHC), SPI and Comparator. The CHARC, DECMD0, DECMD1 and VOL
are audio control related registers. The LVD register is used to monitor IC power with four level setting,
2.4V, 2.7V, 3.6V and 4.1V, the output flag goes high while power is higher. The TMCS register is to select
8 clock sources (4MHz, 2MHz, 1MHz, 500KHz, 250KHz, 125KHz, 62.5KHz and Comparator output) for
timer counter and timer value represented for timer counter or capture timer. The RTML/RTMH registers
are used to access timer data. The XMDx are for indirect RAM access with different addressing composed
by RPT and PAGE. The SPIV register is for power control for SPI interface, and SPIC register is for further
SPI control. The SPIDx registers are used to access data between SPI flash. The Px and PxIO are I/O
ports registers, here x could be A, B, C, D, E or F. As PA, PB, PC, PD, PE and PF are bi-directional I/O
ports, PAIO, PBIO, PCIO, PDIO, PEIO and PFIO are used to determine the direction of each I/O pin.
3.1.1 System Register Address Map
Addr
Name
R/W
Bit
Data
Description
Default
$00
INT0
R/W
[0]
0/1 Disable / Enable BT 0.256ms Interrupt
Disable
[1]
0/1 Disable / Enable BT 0.512ms Interrupt
Disable
[2]
0/1 Disable / Enable BT 1.024ms Interrupt
Disable
[3]
0/1 Disable / Enable BT 16.384ms Interrupt
Disable
$01
INT1
R/W
[0]
0/1 Disable / Enable Timer Interrupt
Disable
[1]
0/1 Disable / Enable PH Interrupt
Disable
[2]
0/1 Disable / Enable SPI Interrupt
Disable
[3]
0/1 Disable / Enable COMP. Interrupt
Disable
$02
INTF0
R/W
[0]
0/1 BT 0.256ms Interrupt Flag, write 0 to clear flag
0
[1]
0/1 BT 0.512ms Interrupt Flag, write 0 to clear flag
0
[2]
0/1 BT 1.024ms Interrupt Flag, write 0 to clear flag
0
[3]
0/1 BT 16.384ms Interrupt Flag, write 0 to clear flag
0
$03
INTF1
R/W
[0]
0/1 Timer Flag, write 0 to clear flag
0
[1]
0/1 PH Flag, write 0 to clear flag
0
[2]
0/1 SPI Flag, write 0 to clear flag
0
[3]
0/1 COMP. Flag, write 0 to clear flag
0
