NY6 User Manual
Ver 1.3 2019/03/28
20
2.6.2 RAM
There are 6 pages of RAM, each page of RAM contains 56 nibbles. It’s total 336 nibbles. The page of
RAM defined by MPG (PAGE0~5), and its initial is PAGE0. Memory Registers of RPT0~5 and ROD1~2
will occupy address space from 0x00 to 0x07. Moreover, this address
space of PAGE0~5 are mapped to the same dedicated registers. As
consequence, the address space of PAGE0~5 RAM which can be used by
programmer is 0x08~0x3F.
In addition to the immediate addressing mode, the indexed addressing
mode is also supported. The page and address of the indexed RAM
should be stored into {PAGE, RPT1[1:0], RPT0} or {PAGE, RPT3[1:0],
RPT2} first, and users can read from or write in the XMD0/XMD1 memory
register to realize the indexed RAM access.
2.7 I/O Ports
There are at most 24 I/O pins, designated as PAx through PFx, and x=0~3. All the I/O pins are bi-
directional. An individual and independent register bit can determine the direction of each I/O pin. These
register bits are PAIO (SFR $15), PBIO (SFR $17), PCIO (SFR $19), PDIO (SFR $1B), PEIO (SFR $1D)
and PFIO (SFR $1F).
Using as input pin of each I/O, there are 3 kinds of mask option. Users can select input with pull-high
resistor, input without pull-high resistor, or input with register-controlled pull-high resistor (high-to-low
wakeup only). If users want to enable/disable pull-high resistor by register during program execution, only
high-to-low level change on this pin can wakeup NY6. On the other hand, if the pull-high resistor is fixed by
option, either high-to-low or low-to-high level change on this pin can wakeup NY6. Users can refer
Chapter
3.14 I/O Ports Register
for details.
The pull-high resistor of all the I/O pins has two kinds of option: weak and strong. The weak one is about
1.2MΩ@3V for normal application and the strong one is about 100KΩ@3V usually for key matrix function.
When users decide this option, the same strength of pull-high resistor will be applied to all I/O pin.
Using as output pin of each I/O, there are 3 kinds of mask option. Users can select output with normal drive
current and normal sink current, normal drive current and large sink current, or normal drive current and
constant sink current.
Some I/O ports can also be optioned as specific application, i.e. External reset pin (PA3), an infrared (IR)
output pin (PA2), inputs of voltage comparator (PA0/PA1) or SPI associated control pins (PB0~3). A reset
pin can possess a pull-high resister or not according to the mask option, which is used to enable/disable
the pull-high resistor of I/O pin.
Address
ROM
0x00
0x07
Memory
Registers
0x08
0x3F
General SRAM
56 nibbles
Page 0 ~ 5
