NXP Semiconductors P89LPC980, Руководство пользователя

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UM10346_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 01 — 2 November 2009 55 of 132
NXP Semiconductors
UM10346
LPC980/982 User manual
100 0 00 High frequency crystal Watchdog oscillator
/DIVM
01 Medium frequency crystal
10 Low frequency crystal
11 Watchdog oscillator /DIVM
1 00 High frequency crystal Internal RC oscillator
01 Medium frequency crystal
10 Low frequency crystal
11 Internal RC oscillator
101 x xx undefined undefined
110 x xx undefined undefined
111 0 00 External clock input External clock input
/DIVM
01
10
11 External clock input /DIVM
1 00 External clock input Internal RC oscillator
01
10
11 Internal RC oscillator
Table 42. Real-time Clock Control register (RTCCON - address D1h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RTCF RTCS1 RTCS0 - - - ERTC RTCEN
Reset 0 1 1 x x x 0 0
Table 43. Real-time Clock Control register (RTCCON - address D1h) bit description
Bit Symbol Description
0 RTCEN Real-time Clock enable. The Real-time Clock will be enabled if this bit is logic 1.
Note that this bit will not power-down the Real-time Clock. The RTCPD bit
(PCONA.7) if set, will power-down and disable this block regardless of RTCEN.
1 ERTC Real-time Clock interrupt enable. The Real-time Clock shares the same
interrupt as the watchdog timer. Note that if the user configuration bit WDTE
(UCFG2.7) is logic 0, the watchdog timer can be enabled to generate an
interrupt. Users can read the RTCF (RTCCON.7) bit to determine whether the
Real-time Clock caused the interrupt.
2:4 - reserved
5 RTCS0 Real-time Clock source select (see Table 41 ).
6 RTCS1
7 RTCF Real-time Clock Flag. This bit is set to logic 1 when the 23-bit Real-time Clock
reaches a count of logic 0. It can be cleared in software.
Table 41. Real-time Clock/System Timer clock sources
…continued
FOSC2:0 RCCLK RTCS1:0 RTC clock source CPU clock source