NXP Semiconductors P89LPC980, Руководство пользователя

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UM10346_1 © NXP B.V. 2009. All rights reserved.
User manual Rev. 01 — 2 November 2009 21 of 132
NXP Semiconductors
UM10346
LPC980/982 User manual
XDATA — ‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory
space addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this
space could be implemented on-chip. The P89LPC982 has 256 bytes of on-chip XDATA
memory, plus extended SFRs located in XDATA.
CODE — 64 kB of Code memory space, accessed as part of program execution and via
the MOVC instruction. The P89LPC980/982 has 4 kB/8 kB of on-chip Code memory.
2. Clocks
2.1 Enhanced CPU
The P89LPC980/982 uses an enhanced 80C51 CPU which runs at six times the speed of
standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most
instructions execute in one or two machine cycles.
2.2 Clock definitions
The P89LPC980/982 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock
sources and can also be optionally divided to a slower frequency (see Figure 7 and
Section 2.10 “CPU Clock (CCLK) modification: DIVM register” ). Note: f
osc
is defined as
the OSCCLK frequency.
CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two or
four CCLK cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.The clock doubler option, when
enabled, provides an output frequency of 14.746 MHz.
PCLK — Clock for the various peripheral devices and is
CCLK
⁄
2
.
2.2.1 Oscillator Clock (OSCCLK)
The P89LPC980/982 provides several user-selectable oscillator options in generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are configured when the flash is programmed and include an
on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external
crystal, or an external clock source.
Table 4. Data RAM arrangement
Type Data RAM Size (bytes)
DATA Directly and indirectly addressable memory 128
IDATA Indirectly addressable memory 256
XDATA Auxiliary (‘External Data’) on-chip memory that is accessed using
the MOVX instructions (P89LPC982) 256