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Страница: 24 / 28

Figure 36. CAN_CLK in Tree

XOSC and

PLL0_PHI

are already configured from the previous section, so there is no need to repeat those steps.

CAN_CLK

traces back to

AUX Clock Selector 8

, which currently follows the IRCOSC. Change

AUX Clock Selector 8

to follow XOSC.

Figure 37. CAN_CLK changed to follow XOSC

Next, enable

CAN_CLK

block and set the

PBRIDGEx_CLK

divider. Set the associated

Clk En

block to 1 and the

CAN_CLK

divider

to 0: 40 MHz/(0+1) = 40 MHz. So, in closing, this example has achieved its goal: a 40 MHz XOSC driving a PLL that produces
an output of 200 MHz, and from there the PLL running

PBRIDGE_x_CLK

at 50 MHz and the

CAN_CLK

at 40 MHz, sourced from

the XOSC. Finally, the

PBRIDGE_x_CLK

and

CAN_CLK

drive the FlexCAN module.

NXP Semiconductors

Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock

MPC574xR Clock Calculator Guide, Rev. 5, October 2018

Application Note

24 / 28

Содержание MPC5743R

Страница 1: ...lculator The clock calculator makes use of macros to perform functions like resetting the spreadsheet to initial values configuring all clock frequencies to the maximum allowable settings and copying...

Страница 2: ...requency cells Values that are out of range will be rejected and the user will receive an error message Invalid clock domain frequencies that arise from valid input values and legal but improper divid...

Страница 3: ...Tree is the centerpiece of the tool This tab is the starting point for all clock frequency calculations It is organized to resemble the MPC5746R clock tree as presented in the following figure NXP Sem...

Страница 4: ...following figure shows in part the diagram s clock tool counterpart The difference between the two is that the latter is interactive NXP Semiconductors Clock calculator design MPC574xR Clock Calculat...

Страница 5: ...ured in the PLL0 tab PER_CLK selects from these three clock sources by selecting the value of the AUX Clock Selector 0 block Then finally the selected signal is divided by the PER_CLK prescaler value...

Страница 6: ...also referred to simply as XTAL If the XOSC Select block selects XTAL XOSC will derive its frequency from the external oscillator XTAL block Alternatively a waveform can be driven directly to the EXT...

Страница 7: ...if all modules using it can fit within a single window without having to scroll The frequencies on this tab are not meant to be modified and are dependent on frequency values in the Tree tab 2 4 LFAS...

Страница 8: ...heet Figure 11 LFAST block diagram Since the LFAST signal must be generated from an input clock of 10 13 20 or 26 MHz this tool blocks any input from the signal RF_REF other than these four values RF_...

Страница 9: ...0 and the user would know to change the input 2 5 PLLx PLL0 and PLL1 are visual abstractions of the PLL digital interface as in the next figure Figure 13 PLL0 control The input source of PLL0 and PLL1...

Страница 10: ...HI or PLL0_PHI1 The reference table will then calculate the output frequency for each MFD and RFD setting Like in the other sections frequencies are color coded to define which values are valid and wh...

Страница 11: ...RUN_MC among the MC_ME_ MODE _MC registers should be set to 0xX0XX00F4 Assuming the instances of X are 0 the resulting S32DS C code would be MC_ME DRUN_MC R 0x000000F4 Summary also includes an overvie...

Страница 12: ...o auxiliary clocks The dynamic C code in these functions depend on tool settings just like the register summary These functions can be copied and pasted to a source file via Ctrl C Ctrl V or by clicki...

Страница 13: ...The values in its tables are based on the MPC5746R s datasheet and reference manual and therefore should not be modified by the user The following figure is a screenshot of the Limits tab NXP Semicon...

Страница 14: ...LL The example will not only show the correct configurations but also how the tool responds if improper configurations are attempted When configuring clocks for a module start at Peripheral Domains As...

Страница 15: ...plains what each available value represents As shown in the figure PBRIDGE_x_CLK is currently enabled and sourced from the 16 MHz IRCOSC divided by 1 for a final frequency of 16 MHz Since the only way...

Страница 16: ...empt to enter 7 MHz to the XOSC frequency cell A dialog box appears notifying the user that the value is not accepted when he she tries to click away from the cell Figure 22 Invalid frequency input Se...

Страница 17: ...circles the blocks that represent the XOSC crystal the XOSC controller and the effective frequency as sensed by AUX Clock Selector 4 and CMU_0 Figure 24 Actual XOSC frequency with source turned off N...

Страница 18: ...urned on 3 1 2 Configure PLL0 Follow the XOSC path to AUX Clock Selector 3 Change the AUX Clock Selector 3 value to 1 so that PLL0 sources from XOSC as shown in the figure below NXP Semiconductors Clo...

Страница 19: ...rce frequency Figure 27 PLL0 calculator Configure the dividers to achieve 200 MHz The correct configuration can be achieved by trial and error but the MPC574xR Clock Calculator provides a lookup table...

Страница 20: ...equency of 40 MHz and a PREDIV of 2 This example will use a MFD of 20 and a RFD of 2 but before configuring the PLL0 tab it is worth noting what happens if the output PLL frequency is out of range In...

Страница 21: ...xt figure the output PLL0_PHI is 200 MHz and the cell remains unshaded meaning the configuration fits within spec Figure 31 PLL0_PHI configured to 200 MHz Go back to Tree to observe that the PLL0_PHI...

Страница 22: ...rogressive clock switch before propagating to the various system clock domains PCFS takes IRCOSC in this diagram because its logic is organized in terms of IRCOSC cycles You can find more information...

Страница 23: ...maximum allowable PBRIDGE_x_CLK frequency of 50 MHz The tool will highlight the PBRIDGE_x_CLK cell red to signify that such a frequency is not allowed as shown in the following figure Figure 35 PBRIDG...

Страница 24: ...he associated Clk En block to 1 and the CAN_CLK divider to 0 40 MHz 0 1 40 MHz So in closing this example has achieved its goal a 40 MHz XOSC driving a PLL that produces an output of 200 MHz and from...

Страница 25: ...k_Init and InitPeriClkGen provide dynamic clock generation C code The code will configure the clocks to the settings as configured in this clock calculator It can be copied and pasted to a source file...

Страница 26: ...Conclusion This application note gives an overview of the MPC5746R interactive clock calculator It seeks to simplify clock configurations in the form of a graphical tool so that a user can more easil...

Страница 27: ...74xR_Clock_Calculator file 2 December 2017 Updated the associated AN12020SW 3 January 2018 Editorial updates 4 February 2018 Updated the associated AN12020SW 5 October 2018 Updated the associated AN12...

Страница 28: ...ITAG I2C BUS ICODE JCOP LIFE VIBES MIFARE MIFARE CLASSIC MIFARE DESFire MIFARE PLUS MIFARE FLEX MANTIS MIFARE ULTRALIGHT MIFARE4MOBILE MIGLO NTAG ROADLINK SMARTLX SMARTMX STARPLUG TOPFET TRENCHMOS UCO...

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