Figure 39. Sysclk_Init after example
To summarize, this example has achieved its goal: a FlexCAN whose bus interface and module clocks are driven by a PLL-sourced
PBRIDGE_x_CLK
at 50 MHz. The 50 MHz
PBRIDGE_x_CLK
is divided down from a 200 MHz PLL output; and the PLL output
in turn is driven by the 40 MHz external oscillator. And finally, the FlexCAN’s protocol clock is driven by a 40 MHz XOSC-sourced
CAN_CLK
.
4 Conclusion
This application note gives an overview of the MPC5746R interactive clock calculator. It seeks to simplify clock configurations in
the form of a graphical tool so that a user can more easily visualize the device’s clock signals’ propagation. There are similar clock
calculators for other NXP products, including the MPC574xG and S32K14x. Visit the
to find more of these tools.
5 Revision history
Rev. No.
Date
Substantive Change(s)
0
July 2017
Initial version
Table
continues
on the next
page...
NXP Semiconductors
Conclusion
MPC574xR Clock Calculator Guide, Rev. 5, October 2018
Application Note
26 / 28
