Figure 26. PLL0 source to XOSC
Next, configure PLL0. Click on the
PLL0
block to forward automatically to the
PLL0
tab. This is the tab that sets up the
PLL0_PHI
frequency. The
PLL0 Input
block of the figure below shows that PLL0 detects the 40 MHz XOSC as its source frequency.
Figure 27. PLL0 calculator
Configure the dividers to achieve 200 MHz. The correct configuration can be achieved by trial and error, but the MPC574xR Clock
Calculator provides a lookup table in the
pll0_phi
tab, as shown in the following figure.
NXP Semiconductors
Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock
MPC574xR Clock Calculator Guide, Rev. 5, October 2018
Application Note
19 / 28
