3.3 Observe the registers
The final register summary table, as displayed in
Summary
, is shown in the following figure. Note that most of these registers
would not have to be written in code to achieve the setup that this example just configured. For example, the register
MC_CGM_AC0_DC0 would not have to be included, since Auxiliary Clock 0 was untouched. Registers that would have to be
written would be ones like PLLDIG_PLL0DV and MC_CGM_AC8_SC.
Figure 38. Register summary after configuration
3.4 Copy the code
Sysclk_Init
and
InitPeriClkGen
provide dynamic clock generation C code. The code will configure the clocks to the settings as
configured in this clock calculator. It can be copied and pasted to a source file. The following figure shows
Sysclk_Init
as configured
by this example. The solid-bordered highlight around the function means that the code has been copied with the
Copy Code
button; a regular Ctrl+C causes a dashed-bordered highlight. In both cases, the code can be pasted into a source with a regular
Ctrl+V.
NXP Semiconductors
Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock
MPC574xR Clock Calculator Guide, Rev. 5, October 2018
Application Note
25 / 28
