NXP Semiconductors MAC57D5 Series, Руководство пользователя, Страница: 18 / 30

Table 16. VIU connector pinout (continued)
20
VIU_DATA_15 VIU Pixel Data Input
21
VIU_DATA_0 VIU Pixel Data Input
22 VIU_DATA_1 VIU Pixel Data Input
23 VIU_DATA_2 VIU Pixel Data Input
24
VIU_DATA_3 VIU Pixel Data Input
25
VIU_DATA_4 VIU Pixel Data Input
26 VIU_DATA_5 VIU Pixel Data Input
27 VIU_DATA_6 VIU Pixel Data Input
28
VIU_DATA_7 VIU Pixel Data Input
29
GND
30 VIU_PCLK VIU Pixel Clock Input
31 GPIO
32
VIU_HSYNC VIU Horizontal Sync Input
33
VIU_VSYNC VIU Vertical Sync Input
34 VIU_DE VIU Data Enable Input
35 GPIO
36
GND
37
SDA I2C Serial Data Output
38 SCL I2C Serial Clock Output
39 VIU_FID VIU Frame ID Input
40
VIU_RST GPIO
NOTE
For MAC57D5-208DC daughterboard, some ENET and VIU data lines are shared from
the MCU, each interface is separated by two 0 resistors, by default the VIU data lines are
disabled.
10.4 LVDS interface
The LVDS module on MAC57D5-516DC is available in a 30‐pin connector [DF19G-30P-1H(54)].
Table 17. LVDS interface
J20 – LVDS Interface
Pin No. Signal Description
1 LVDS_BACKLITE_ON PM10
2 P3V3_LVDS 3.3 V
3
4
5
LVDS_BACKLITE_BRIGHTNESS PN13
6 OLDI_N3 Pixel Data
Table continues on the next page...
Graphics display and video interfaces
MAC57D5xx Customer Evaluation Boards, Rev. 0, 05/2016
18 Freescale Semiconductor, Inc.