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14.2.6 Sticky System Reset Status Register 0 (RCM_SSRS0)
This register includes status flags to indicate all reset sources since the last POR, LVD or
VLLS Wakeup that have not been cleared by software. Software can clear the status flags
by writing a logic one to a flag.
Address: 4007_F000h base + 8h offset = 4007_F008h
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
1
0
0
0
0
0
1
0
RCM_SSRS0 field descriptions
Field
Description
7
SPOR
Sticky Power-On Reset
Indicates a reset has been caused by the power-on detection logic. Because the internal supply voltage
was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset
occurred while the internal supply was below the LVD threshold.
0
Reset not caused by POR
1
Reset caused by POR
6
SPIN
Sticky External Reset Pin
Indicates a reset has been caused by an active-low level on the external RESET pin.
0
Reset not caused by external reset pin
1
Reset caused by external reset pin
5
SWDOG
Sticky Watchdog
Indicates a reset has been caused by the watchdog timer timing out.This reset source can be blocked by
disabling the watchdog.
0
Reset not caused by watchdog timeout
1
Reset caused by watchdog timeout
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
SLOL
Sticky Loss-of-Lock Reset
Indicates a reset has been caused by a loss of lock in the MCG PLL. See the MCG description for
information on the loss-of-clock event.
0
Reset not caused by a loss of lock in the PLL
1
Reset caused by a loss of lock in the PLL
2
SLOC
Sticky Loss-of-Clock Reset
Table continues on the next page...
Reset memory map and register descriptions
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
348
NXP Semiconductors
Содержание K22F series
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