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NXP Semiconductors

Quick start ADC1610S series (F1 or F2 versions)

Quick start

© NXP B.V. 2011. All rights reserved.

Quick start

Rev. 5 — January 2011

15 of 28

Fig 8. SW_ADC_1_r02: “Info” page

The HSDC-EXTMOD is not yet initialized, so the embedded PLL (LMK03001 in this example) is not
locked. Initialization is only required for acquisition purpose.

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Содержание ADC1610S Series

Страница 1: ...1610S series F1 or F2 versions Demonstration board for ADC1610S series January 2011 Document information Content PCB2131 1 Demonstration board ADC Converter This document describes how to use the demo...

Страница 2: ...versions Quick start Revision history Rev Date Description 1 20081001 Initial version 2 20090518 Update 3 20090610 Add SPI software description 4 20100519 Add HSDC extension module acquisition system...

Страница 3: ...e ADC1610S Fig 1 1 1 ADC1610S setup Register programming USB SPI DC adaptor connected to mains LOGIC ANALYZER Output data DO LSB to Dxx MSB DAV for synchro OTR Out of range PRESENTED CONFIGURATION 2Vp...

Страница 4: ...LVDS DDR digital outputs nnections to measure ADC1610S PRESENTED CONFIGURATI 2Vpp input full scale Single Sine wave clock signal Input common mode from IC Binary ADC output SPI Mode EXTENTION MODULE...

Страница 5: ...owered either with a 3 VDC and 1 8 3 VDC power supplies or a 5V DC View hange ST9 and ST10 position accordingly Power supply 3 VDC Change ST9 and ST10 position accordingly Power supply 1 8 VDC Power s...

Страница 6: ...ing J2 CLKP connector Single ended clock input signal 50 matching with a transformer J3 CLKM connector Grounded on that demoboard 1 5 Output signals in CMOS version D0 to D15 DAV OTR The digital outpu...

Страница 7: ...start Rev 5 January 2011 7 of 28 1 6 Output signals in LVDS DDR version The digital output signal is available in binary 2 s complement or gray format A Data Valid Output clock DAV is provided by the...

Страница 8: ...All rights reserved Quick start Rev 5 January 2011 8 of 28 1 7 SPI Mode The ADC1610S can be controlled either by a Serial Peripheral Interface SPI or by PIN Table 5 SPI Interface Name Function View J...

Страница 9: ...3 2 A REFERENCE SIGNAL Typical 10 MHz SIGNAL GENERATOR USB SPI MODULE PRESENTED CONFIGURATION Acquisition board External reference signal LVDS DDR 16 bit input stream CMOS 2 16 bit channels input LVD...

Страница 10: ...is section the specific requirement for the use with ADC1610S demo board will be shown For more details on the HSDC EXTMOD01 DB please contact dataconverter support nxp com 2 1 HSDC extension module h...

Страница 11: ...conductors Quick start ADC1610S series F1 or F2 versions Quick start NXP B V 2011 All rights reserved Quick start Rev 5 January 2011 11 of 28 Fig 4 HSDC extension module HE14 CMOS hardware schematic o...

Страница 12: ...CMOS outputs configuration for which connection is straightforward together with a supply extension module release A for the ADC1610S demo board Fig 5 Evaluation set up measurement with ADC1610S CMOS...

Страница 13: ...guration for which connection is straightforward together with a supply extension module release A for the ADC1610S demo board Fig 6 Evaluation set up measurement with ADC1610S CMOS and HSDC extension...

Страница 14: ...display information as can be seen on following window Fig 7 SW_ADC_1_r02 start up screen NXP Banner Button will display your default internet browser to the NXP data converter home page REFRESH allo...

Страница 15: ...uick start NXP B V 2011 All rights reserved Quick start Rev 5 January 2011 15 of 28 Fig 8 SW_ADC_1_r02 Info page The HSDC EXTMOD is not yet initialized so the embedded PLL LMK03001 in this example is...

Страница 16: ...erved Quick start Rev 5 January 2011 16 of 28 3 3 1 ADC SPI programming Functional Registers page The page displays all SPI registers for ADC1610S series Fig 9 SW_ADC_1_r02 ADC Functional Registers pa...

Страница 17: ...cking on the Read all registers button and will display the result in the table below Fig 10 SW_ADC_1_r02 ADC Read Registers page When all registers have been read it is possible to save the data to a...

Страница 18: ...allows downloading configuration data to the device registers It is not necessary to have a file that has the whole set of registers listed The only restriction is regarding the formatting of the fil...

Страница 19: ...are located in the Nyquist zone Enter your analog and sampling frequencies in field Indicate the number of samples to be acquired as well as the fixed parameter for the coherency calculation Fs in ou...

Страница 20: ...n It will initialized the HSDC EXTMOD board FPGA is ready red LED is flashing on and off PLL embedded is locked green LED is on indicate whether Fin or Fs are coherent or not field if signals are cohe...

Страница 21: ...Bc dBc dBFS dBc dBFS dBc dBc dBc dBc dBc dBc ADC1610S test ADC0 5 00 122 88 0 96 11 28 69 79 69 67 70 75 84 62 85 58 85 27 104 62 100 12 103 67 86 57 112 7 Note that while acquisition is running any o...

Страница 22: ...k start Rev 5 January 2011 22 of 28 3 3 5 2 Reorganized signal The reorganized signal displays the reconstructed sine wave from coherency calculation corresponding to 1 period of the input signal Fig...

Страница 23: ...ructed signal The unreconstructed signal displays the unreconstructed sine wave corresponding to the whole number of period being acquired following the coherency rule Fig 16 SW_ADC_1_r02 Acquisition...

Страница 24: ...1 24 of 28 3 3 5 4 Histogram The histogram graph shows the distribution of output codes This graph shows which code is present and if there is any missing code in the conversion range Fig 17 SW_ADC_1_...

Страница 25: ...page This page will give practical information related to software and hardware settings Fig 18 SW_ADC_1_r02 Info page The information visible on this page is board serial number HSDC software release...

Страница 26: ...uch that it follows the equation above To do this iterative calculation one has to decide whether Fin or Fs is fixed To illustrate this process let s consider our current example with Fin 5 MHz Fs 122...

Страница 27: ...tart ADC1610S series F1 or F2 versions Quick start NXP B V 2011 All rights reserved Quick start Rev 5 January 2011 27 of 28 5 Notes For any question feel free to contact us at the following e mail dat...

Страница 28: ...igital outputs 4 1 3 Power supply 5 1 4 Input signals IN CLK 5 1 5 Output signals in CMOS version D0 to D15 DAV OTR 6 1 6 Output signals in LVDS DDR version 7 1 7 SPI Mode 8 1 8 SPI program 8 2 HSDC e...

Страница 29: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information NXP ADC1610S125F1 DB 598 ADC1610S125F2 DB 598...

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