Nvis 5586A
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Whenever a number of devices interrupt a CPU at a time, and if the processor is able to
handle them properly, it is said to have multiple interrupt processing capability. In 8086s,
there are two interrupt pins, NMI and INTR.
The NMI is a non maskable interrupt input pin which means that any interrupt request at
NMI input cannot be masked or disabled by any means. The INTR is of 256 types. The INTR
types may be from 00 to FFH. If more than one type of INTR interrupt occurs at a time, then
an external chip called Programmable interrupt controller is required to handle them.
Interrupt Service Routines (ISRs) are the programs to be executed by interrupting the main
program execution of the CPU, after an interrupt request appears. After the execution of ISR,
the main program continues its execution further from the point at which it was interrupted.
Broadly there are two types of interrupt in the 8086 microprocessor. The first out of them is
external interrupt and second is internal interrupt. In external interrupt, an external device or
a signal interrupts the processor from outside or, in other words, the interrupt is generated
outside the processor, for example, a keyboard interrupt. The internal interrupt, on the other
hand, is generated internally by the processor circuit, or by the execution of an interrupt
instruction. The examples of this type are divide by zero interrupt, overflow interrupt,
interrupts due to INT instructions, etc.
Non-Maskable Interrupt
The processor 8086 has a non maskable interrupt input pin (NMI) that has the highest
priority among the external interrupts. TRAP is an internal interrupt having the highest
priority amongst all the interrupts except the Divide by Zero (Type0) exception.
The NMI pin should remain high for at least two clock cycles and is not needed to be
synchronized with the clock for being sensed. When NMI is activated, the current instruction
being executed is completed, and then the NMI is served.
Maskable Interrupts
The processor can inhibit certain types of interrupts by use of a special interrupt mask bit.
This mask bit is part of the flags/condition code register, or a special interrupt register. In the
8086 microprocessor if this bit is clear, and an interrupt request occurs on the Interrupt
Request input, it is ignored.
The processor 8086 also provides a pin INTR, which has lower priority as compared to NMI.
Further the priorities, within the INTR types are decided by the type of the INTR signal,
which is to be passed to the processor through data bus by some external device like the
Programmable Interrupt Controller (8255).
The INTR signal is level triggered and can be
masked by resetting the interrupt flag. It is internally synchronized with the high transition of
CLK. For the INTR signal, to be responded to in the next instruction cycle, it must go high in
the last clock cycle of the current instruction or before that. The INTR requests appearing
after the last clock cycle of the current instruction will be responded to after the execution of
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