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Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transaction
cycles. Select Enabled to support compliance with PCI specification version 2.1
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4.8 Integrated Peripherals
Figure 4-6 : BIOS- Integrated Peripherals
On-Chip IDE Device
The system chipset contains IDE HDD Block mode, and a PCI IDE interface with
support for two IDE Primary (Master & Slave) PIO’s and two IDE Primary (Master &
Slave) UDMA’s, and two IDE Secondary (Master & Slave) PIO’s and two IDE Second-
ary (Master & Slave) UDMA’s. Select Enabled to activate the primary and/or second-
ary IDE interface. Select Disabled to deactivate this interface if you install a primary
and/or secondary add-in IDE interface.
USB Controller
Select Enabled if your system contains a Universal Serial Bus controller and you have
USB peripherals.
Содержание PEAK 7220VL2G
Страница 1: ...www nexcom com Single Board Computer User Manual 2003 08 Edition ...
Страница 5: ...4 Chapter 1 General Information Chapter 1 General Information ...
Страница 11: ...10 Chapter 2 Jumper Switch Settings ...
Страница 16: ...2 4 Jumper Setting 15 Mainboard ...
Страница 17: ...16 Daughterboard ...
Страница 18: ...17 daughterboard ...
Страница 19: ...18 ...
Страница 20: ...19 ...
Страница 21: ...Chapter 3 Expansion Capabilities 20 ...
Страница 27: ...26 Chapter 4 Award BIOS Setup ...
Страница 51: ...50 Chapter 5 Driver Installation ...