Technical Information 1-13
Cache Controller, Address Logic, Data Controller
The Golden Gate PT80C732 and PT80C733 Pico Power controller provides a dual-chip
structure that connect the Pentium processor to the industry-standard 486 bus. The chip in-
creases data reliability by integrating the following:
8-level write buffer
extends battery life and efficient thermal management
improved performance for DRAM and VL bus peripherals.
System Logic, IDE Interface, Peripheral Controller
The PT86C718
Pico Power chip consists of
a 176-pin thin-quad flat-package. This chip
controller supports fast graphics and I/O processing. The system logic controller adds the
following features:
built-in level 2 cache controller
integrated active power management
integrated battery management
high performance DRAM controller.
Flash ROM
The N28F020 flash ROM is a 32-pin, plastic lead chip carrier (PLCC). The chip allows easy
updates to the system's BIOS if needed. More specifically, the ROM is flashed electroni-
cally, installing the latest BIOS revisions to the system. It is possible to reprogram the BIOS
up to 100,000 times. See Section 2, Setup and Operation, for BIOS update procedures.
The N28F020 provides the system upgrade capability as well as the following:
256 KB memory
Quick-Pulse Programming Algorithm
150 nanoseconds (ns) maximum access time
ETOX Nonvolatile flash technology
CMOS low power consumption
