User’s Manual U16896EJ2V0UD
603
CHAPTER 21 CLOCK MONITOR
21.1 Function
The clock monitor samples the main clock by using the internal oscillation clock and generates a reset signal
(CLMRES) when oscillation of the main clock is stopped.
After reset is released, the CPU operates on internal oscillation clock.
Once the operation of the clock monitor has been enabled by the CLM.CLME bit, it can be stopped only by reset.
The clock monitor automatically stops under the following conditions.
•
When the oscillation stabilization time is counted after the STOP mode has been released
•
When the main clock is stopped (PCC.MCK bit = 1 when subclock operates and PCC.CLS bit = 0 when main
clock operates)
•
When the sampling clock (internal oscillation clock) is stopped
•
When the CPU operates on internal oscillation clock
21.2 Registers
(1) Clock monitor mode register (CLM)
The CLM register is a special register that can be written only by a combination of specific sequences (refer to
3.4.7 Special registers
).
The CLM register is used to select the operation mode of the clock monitor.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
Disable clock monitor operation
Enable clock monitor operation
CLME
0
1
Enable/disable of clock monitor operation
CLM
0
0
0
0
0
0
CLME
After reset:
00H R/W
Address:
FFFFF870H
< >
Caution Once the CLME bit has been set to 1, it cannot be cleared to 0 by any means other than reset.
Содержание V850ES/KE1+
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