CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0
User’s Manual U16896EJ2V0UD
238
7.4 Operation
7.4.1 Interval timer operation
If the TMC01.TMC013 and TMC01.TMC012 bits are set to 11 (clear & start mode entered upon a match between
the TM01 register and the CR010 register), the count operation is started in synchronization with the count clock.
When the value of the TM01 register later matches the value of the CR010 register, the TM01 register is cleared to
0000H and a match interrupt signal (INTTM010) is generated. This INTTM010 signal enables the TM01 register to
operate as an interval timer.
Remarks 1.
For the alternate-function pin settings, refer to
Table 4-12 Settings When Port Pins Are Used for
Alternate Functions
.
2.
For enabling the INTTM010 interrupt, refer to
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING
FUNCTION
.
Figure 7-2. Block Diagram of Interval Timer Operation
16-bit counter (TM01)
CR010 register
Operable bits
TMC013, TMC012
Count clock
Clear
Match signal
INTTM010 signal
Figure 7-3. Basic Timing Example of Interval Timer Operation
TM01 register
0000H
Operable bits
(TMC013, TMC012)
Compare register
(CR010)
Compare match interrupt
(INTTM010)
N
11
00
N
N
N
N
Interval
(N + 1)
Interval
(N + 1)
Interval
(N + 1)
Interval
(N + 1)
Содержание V850ES/KE1+
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