CHAPTER 5 CLOCK GENERATION FUNCTION
User’s Manual U16896EJ2V0UD
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5.5.3 Usage
(1) When PLL is used
•
After reset has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default mode is
the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1).
•
To set the STOP mode in which the main clock is stopped, or to set the IDLE mode, first select the clock-
through mode and then stop the PLL. To return from the IDLE or STOP mode, first enable PLL operation
(PLLON bit = 1), and then select the PLL mode (SELPLL bit = 1).
•
To enable the PLL operation, first set the PLLON bit to 1, wait for 200
μ
s, and then set the SELPLL bit to 1.
To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8 clocks or more, and then
stop the PLL (PLLON bit = 0).
(2) When PLL is not used
•
The clock-through mode (SELPLL bit = 0) is selected after reset has been released, but the PLL is
operating (PLLON bit = 1) and must therefore be stopped (PLLON bit = 0).
Remark
The PLL is operable in the IDLE mode. To realize low power consumption, stop the PLL. Be sure
to stop the PLL when shifting to the STOP mode.
Содержание V850ES/KE1+
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