CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
User’s Manual U15331EJ4V1UD
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(4) 8-bit H width compare registers 60 and 61 (CRH60, CRH61)
In carrier generator mode and PPG output mode, the high-level width of timer output is set by writing a value
to CRH6n. This 8-bit register is used to continually compare the value set to CRH6n with the count value in
8-bit timer counter 6n (TM6n) and to issue an interrupt request (INTTM6n) when a match occurs.
CRH6n is set with an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
Remark
n = 0, 1
(5) 8-bit timer counters 50, 60, and 61(TM50, TM60, TM61)
These are 8-bit registers that are used to count the count pulse.
TM50, TM60, and TM61 are read via an 8-bit memory manipulation instruction.
RESET input sets these register values to 00H.
TM50, TM60, and TM61 are cleared to 00H under the following conditions.
(a) Stand-alone mode
•
After reset
•
When TCEmn (bit 7 of 8-bit timer mode control register mn (TMCmn)) is cleared to 0
•
When a match occurs between TMmn and CRmn
•
When the TMmn count value overflows
Remark
mn = 50, 60, 61
(b) Cascade connection mode (TM50 and TM60 are simultaneously cleared to 00H)
•
After reset
•
When the TCE60 flag is cleared to 0
•
When matches occur simultaneously between TM50 and CR50 and between TM60 and CR60
•
When the TM50 and TM60 count values overflow simultaneously
(c) Carrier generator (TM60) and PPG output mode (TM60 and TM61)
•
After reset
•
When the TCE6n flag is cleared to 0
•
When a match occurs between TM6n and CR6n
•
When a match occurs between TM6n and CRH6n
•
When the TM6n count value overflows
Remark
n = 0, 1
(d) PWM output mode (TM50)
•
After reset
•
When the TCE50 flag is cleared to 0
•
When the TM50 count value overflows
Содержание PD789488
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