NEC MultiSync 75F-3, Руководство по обслуживанию

Страница: 53 / 104

SYNC Processor
The functional block diagram of SYNC Processor is shown in Fig. 4. It contains H and V polarity detection
circuit, H and V frequency counter, composite sync signal separation circuit, free-running H and V sync
signal generator, vedio signal generation circuit for burn-in test and clamp pulse generator.
Horizontal Polarity Detect
The horizontal polarity is detected by sampling HIN signal at 5.5~6.5us after rising and falling edge of HIN.
If the result of sampling is low and lasts 192~256us with no change, the polarity is positive (HINPOL=1). If
the result of sampling is high and lasts 192~256us with no change, the polarity is negative (HINPOL=0).
Vertical Polarity Detect
Vertical polarity is detected by sampling VIN level at 2.048ms after rising edge of VIN. If the level is low, the
polarity is positive (VINPOL=1). If the level is high, the polarity is negative (VINPOL=0). But if SEPART bit is
set, the VINPOL bit is “1” because the Vsync from composite signal separator is always positive polarity.
Output Polarity Control
The polarities of HOUT and VOUT are controlled by HOPOL and VOPOL bites. When the bit is set, the
output polarity is positive. When the bit is cleared, the output polarity is negative.
50
Fig.4 Block diagram of sync signal processor