NEC MultiSync 75F-3, Руководство по обслуживанию

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X-ray protection
The X-ray protection input XRAY (pin 2) provides a voltage
detector with a precise threshold. If the input voltage at
XRAY exceeds this threshold for a certain time, then con-
trol bit SOFTST is reset, which switches the IC into protec-
tion mode. In this mode several pins are forced into defined
states:
HUNLOCK (pin 17) is floating
The capacitor connected to HPLL2 (pin 30) is discharged
Horizontal output stage (HDRV) is floating
B+ control driver stage (BDRV) is floating
CLBL provides a continuous blanking signal.
There are two different methods of restarting ways the IC:
1. XSEL (pin 9) is opeb-circuit or connected to ground. The
control bit SOFTST must be set to logic 1 via the I²C-
bus. Then the IC returns to normal operation via soft
start.
2. XSEL (pin 9) is connected to Vcc via an external resistor.
The supply voltage of the IC must be switched off for a
certain period of time, before the IC can be restarted
again using the standard power-on procedure.
Vertical oscillator and amplitude control
This stage is designed for fast stabilization of vertical size
after changes in sync frequency conditions.
The free-running frequency f
fr(v)
is determined by the resis-
tor R
VREF
connected to pin 23 and the capacitor C
VCAP
con-
nected to pin 24. The value of R
VREF
is not only optimized
for noise and linearity performance in the whole vertical
and EW section, but also influences several internal
reference. Therefore the value of R
VREF
must not be
changed. Capacitor C
VCAP
should be used to select the free-
running frequency of the vertical oscillator in accordance
with the following formula:
VCAP
C
VREF
R 10.8
1
fr(V)
f
× ×
=
To achieve a stabilized amplitude the free-running frequency
ffr(v), without adjustment, should be at least 10% lower than
the minimum trigger frequency.
The contributions shown in Table 2 canbe assumed.
63
I²C-bus autosync deflection controller for PC monitors TDA4857
Contributing elements
Minimum frequency offset between f
fr(v)
and
lowest trigger frequency
10%
Spread of IC ±3%
Spread of R
VREF
±1%
Spread of C
VCAP
±5%
Total 19%
Result for 50 to 160Hz application:
Hz 42
1.19
Hz 50
fr(V)
f
= =
The AGC of the vertical oscillator can be disabled by set-
ting control bit AGCDIS via the I²C-bus. Aprecise external
current has to be injected into VCAP (pin 24) to obtain the
correct vertical size. This special application mode can be
used when the vertical sync pulses are serrated (shifted);
this condition is found in some display modes, e.g. when
using a 100Hz up converter for video signals.
Application hint: VAGC (pin 22) has a high input imped-
ance during scan. Therefore, the pin must not be loaded
externally otherwise non-linearities in the vertical output
currents may occur due to the changing charge current
during scan.
Adjustment of vertical size, VGA overscan and EHT
compensation
There are four different ways to adjust the amplitude of the
differential output currents at VOUT1 and VOUT2.
1 Register VGIN changes the vertical size without affect-
ing any other output signal of the IC. This adjustment is
meant for factory alignments.
2 Register VSIZE changes not only the vertical size, but
also provides the correct tracking of all other related
w a v e f o r m s ( s e e s e c t i o n ” Tr a c k i n g o f v e r t i c a l
adjustments”). This register should be used for user
adjustments.
3 For the VGA350 mode register VOVSCN can activate a
+17% step in vertical size.
4 VSMOD (pin 21) can be used for a DC controlled EHT
compensation of vertical size by correcting the differen-
tial output currents at VOUT1 and VOUT2. The EW
waveforms, vertical focus, pin unbalance and parallelo-
gram corrections are not affected by VSMOD.
Table 2 Calculation of f
fr(V)
total spread