FUNCTIONAL DESCRIPTION
CPU
8-bit 6502 compatible CPU operates at 6MHz. Address bus is 16-bit and data bus is 8-bit.
The non-maskable interrupt (/NMI) of 6502 is modified to be maskable and is defined as INT0 with higher
priority. The interrupt request (/IRQ) of 6501 is defined as INT1 with lower priority.
Please refer the 6502 reference menu for more detail.
RAM
512 bytes RAM. Address is located from $0080h to $00FFh and $0180h to $02FFh.
RAM from $0200h to $027Fh and $0280h to $02FFh can be disabled individually to emulate different
RAM size IC. (see Register $0FFFh)
ROM
32768 bytes flash memory for program. Address is located from $8000h to $FFFFh.
The following addresses are reserved for special purpose:
$FFFAh (low byte) and $FFFBh (high byte) : INT0 interrupt vector.
$FFFCh (low byte) and $FFFDh (high byte) : program reset interrupt vector.
$FFFEh (low byte) and $FFFFh (high byte) : INT1 interrupt vector.
System Reset
There are four reset sources of this controller. Fig. 1 shows the block diagram of reset logic.
$0000h
:
$003Fh
Registers
$0040h
:
$007Fh
Reserved
$0080h
:
$00FFh
128 bytes RAM
$0100h
:
$017Fh
Reserved
$0180h
:
$02FFh
384 bytes RAM
$0300h
:
$0FFEh
Reserved
$0FFFh
Configuration Register
$1000h
:
$7FFFh
Reserved
$8000h
:
:
:
$FFFFh
Flash ROM
47
Содержание MultiSync 75F-3
Страница 56: ...DDC Flow Chart 53 ...
Страница 57: ...Master I C Flow Chart 54 ...
Страница 58: ...Master I C restart mode Flow Chart 55 ...
Страница 59: ...Slave I C Flow Chart 56 ...
Страница 61: ...BLOCK DIAGRAM I C bus autosync deflection controller for PC monitors TDA4857 58 ...
Страница 71: ...I C bus autosync deflection controller for PC monitors TDA4857 68 APPLICATION INFORMATION ...
Страница 77: ...74 8 Monolithic triple 13 5nS CRT driver ...
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