CHAPTER 20 INSTRUCTION SET
388
User’s Manual U11302EJ4V0UM
Instruc- Mnemonic
Operands
Bytes
Operation
tion
Group
SUB
A, #byte
2
4
–
A, CY
←
A–byte
×
×
×
saddr, #byte
3
6
8
(saddr), CY
←
(saddr)–byte
×
×
×
A, r
Note 3
2
4
–
A, CY
←
A–r
×
×
×
r, A
2
4
–
r, CY
←
r–A
×
×
×
A, saddr
2
4
5
A, CY
←
A–(saddr)
×
×
×
A, !addr16
3
8
9
A, CY
←
A–(addr16)
×
×
×
A, [HL]
1
4
5
A, CY
←
A–(HL)
×
×
×
A, [HL+byte]
2
8
9
A, CY
←
A–(HL+byte)
×
×
×
A, [HL+B]
2
8
9
A, CY
←
A–(HL+B)
×
×
×
A, [HL+C]
2
8
9
A, CY
←
A–(HL+C)
×
×
×
SUBC
A, #byte
2
4
–
A, CY
←
A–byte–CY
×
×
×
saddr, #byte
3
6
8
(saddr), CY
←
(saddr)–byte–CY
×
×
×
A, r
Note 3
2
4
–
A, CY
←
A–r–CY
×
×
×
r, A
2
4
–
r, CY
←
r–A–CY
×
×
×
A, saddr
2
4
5
A, CY
←
A–(saddr)–CY
×
×
×
A, !addr16
3
8
9
A, CY
←
A–(addr16)–CY
×
×
×
A, [HL]
1
4
5
A, CY
←
A–(HL)–CY
×
×
×
A, [HL+byte]
2
8
9
A, CY
←
A–(HL+byte)–CY
×
×
×
A, [HL+B]
2
8
9
A, CY
←
A–(HL+B)–CY
×
×
×
A, [HL+C]
2
8
9
A, CY
←
A–(HL+C)–CY
×
×
×
AND
A, #byte
2
4
–
A
←
A byte
×
saddr, #byte
3
6
8
(saddr)
←
(saddr) byte
×
A, r
Note 3
2
4
–
A
←
A r
×
r, A
2
4
–
r
←
r A
×
A, saddr
2
4
5
A
←
A (saddr)
×
A, !addr16
3
8
9
A
←
A (addr16)
×
A, [HL]
1
4
5
A
←
A (HL)
×
A, [HL+byte]
2
8
9
A
←
A (HL+byte)
×
A, [HL+B]
2
8
9
A
←
A (HL+B)
×
A, [HL+C]
2
8
9
A
←
A (HL+C)
×
Notes 1.
When the internal high-speed RAM area is accessed or an instruction with no data access.
2.
When an area except the internal high-speed RAM area is accessed.
3.
Except r = A
Remark
One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the processor clock control
register (PCC).
Z
AC CY
Note 2
Note 1
Clocks
Flag
8-bit
operation
Содержание mPD780204
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