13.0 Bus Arbitration and Timing
(Continued)
When in 32-bit mode four additional BSCK cycles are re-
quired per burst. The first bus cycle (T1
Ê
– T4
Ê
) of each burst
is used to output the upper 16-bit addresses. This 16-bit
address is programmed in RSAR0 and RSAR1 and points to
a 64k page of system memory. All transmitted or received
packets are constrained to reside within this 64k page.
FIFO BURST CONTROL
All Local DMA transfers are burst transfers, once the DMA
requests the bus and the bus is acknowledged, the DMA will
transfer an exact burst of bytes programmed in the Data
Configuration Register (DCR) then relinquish the bus. If
there are remaining bytes in the FIFO the next burst will not
be initiated until the FIFO threshold is exceeded. If BACK is
removed during the transfer, the burst transfer will be abort-
ed.
(DROPPING BACK DURING A DMA CYCLE IS NOT
RECOMMENDED.)
TL/F/11157 – 26
where N
e
1, 2, 4, or 6 Words or N
e
2, 4, 8, or 12 Bytes when in byte mode.
INTERLEAVED LOCAL OPERATION
If a remote DMA transfer is initiated or in progress when a
packet is being received or transmitted, the Remote DMA
transfer will be interrupted for higher priority Local DMA
transfers. When the Local DMA transfer is completed the
Remote DMA will rearbitrate for the bus and continue its
transfers. This is illustrated below:
TL/F/11157 – 27
Note that if the FIFO requires service while a remote DMA is
in progress, BREQ is not dropped and the Local DMA burst
is appended to the Remote Transfer. When switching from
a local transfer to a remote transfer, however, BREQ is
dropped and raised again. This allows the CPU or other
devices to fairly contend for the bus.
FIFO AND BUS OPERATIONS
Overview
To accommodate the different rates at which data comes
from (or goes to) the network and goes to (or comes from)
the system memory, the ST-NIC contains a 16-byte FIFO for
buffering data between the bus and the media. The FIFO
threshold is programmable, allowing filling (or emptying) the
FIFO at different rates. When the FIFO has filled to its pro-
grammed threshold, the local DMA channel transfers these
bytes (or words) into local memory. It is crucial that the local
DMA is given access to the bus within a minimum bus laten-
cy time; otherwise a FIFO underrun (or overrun) occurs.
To understand FIFO underruns or overruns, there are two
causes which produce this conditionÐ
1. the bus latency is so long that the FIFO has filled (or
emptied) from the network before the local DMA has
serviced the FIFO.
2. the bus latency or bus data rate has slowed the through-
put of the local DMA to a point where it is slower than the
network data rate (10 Mb/s). This second condition is
also dependent upon DMA clock and word width (byte
wide or word wide).
The worst case condition ultimately limits the overall bus
latency which the ST-NIC can tolerate.
FIFO Underrun and Transmit Enable
During transmission, if a FIFO underrun occurs, the Trans-
mit enable (TXE) output may remain high (active). Generally,
this will cause a very large packet to be transmitted onto the
network. The jabber feature of the transceiver will terminate
the transmission, and reset TXE.
To prevent this problem, a properly designed system will not
allow FIFO underruns by giving the ST-NIC a bus acknowl-
edge within time shown in the maximum bus latency curves
shown and described later.
FIFO at the Beginning of Receive
At the beginning of reception, the ST-NIC stores entire Ad-
dress field of each incoming packet in the FIFO to deter-
43
Obsolete
