16.0 AC Timing Test Conditions
All specifications are valid only if the mandatory isolation is
employed and all differential signals are taken to be at the
AUI side of the pulse transformer.
Input Pulse Levels (TTL/CMOS)
GND to 3.0V
Input Rise and Fall Times (TTL/CMOS)
5 ns
Input and Output Reference
Levels (TTL/CMOS)
1.3V
Input Pulse Levels (Diff.)
b
350 mV to
b
1315 mV
Input and Output
50% Point of
Reference Levels (Diff.)
the Differential
TRI-STATE Reference Levels
Float (
D
V)
g
0.5V
Output Load (See Figure Below)
TL/F/11157 – 50
Note 1:
50 pF, includes scope and jig capacitance.
Note 2:
S1
e
Open for timing tests for push pull outputs.
S1
e
V
CC
for V
OL
test.
S1
e
GND for V
OH
test.
S1
e
V
CC
for High Impedance to active low and
active low to High Impedance measurements.
S1
e
GND for High Impedance to active high and
active high to High Impedance measurements.
Pin Capacitance
T
A
e
25
§
C, f
e
1 MHz
Symbol
Parameter
Typ
Units
C
IN
Input Capacitance
7
pF
C
OUT
Output Capacitance
7
pF
DERATING FACTOR
Output timing is measured with a purely capacitive load of
50 pF. The following correction factor can be used for other
loads: C
L
t
50 pF
a
0.3 ns/pF.
AUI Transmit Test Load
TL/F/11157 – 51
Note:
In the above diagram, the TX
a
and TX
b
signals are taken from the
AUI side of the isolation (pulse transformer). The pulse transformer
used for all testing is the Pulse Engineering PE64103.
67
Obsolete
