July
2009
Rev
0.06
Page 2 of 31
1
....
Overview 3
2
....
Evaluation Kit (SDALTEVK) Contents
3
3
....
Hardware Setup 5
3.1
C
YCLONE
III
D
EVELOPMENT
B
OARD
(M
AIN
B
OARD
)
D
ESCRIPTION
.................................................................... 6
3.2
SDALTEVK
B
OARD
D
ESCRIPTION
................................................................................................................. 8
4
....
Software Setup
9
4.1
I
NSTALLATION
................................................................................................................................................ 9
4.2
S
TARTUP
.................................................................................................................................................... 10
5
....
Evaluating Hardware 13
5.1
T
EST
S
ETUPS
.............................................................................................................................................. 13
5.1.1
Standalone Video Generator Tests ................................................................................................... 13
5.1.2
Genlock Tests .................................................................................................................................... 14
5.1.3
Video Pass-through Tests ................................................................................................................. 15
5.2
T
ERMINAL
B
ASED
SD/HD/3G
SDI
E
VALUATION
............................................................................................ 15
5.2.1
Standalone Mode............................................................................................................................... 16
5.2.2
Pass-through Mode ........................................................................................................................... 17
5.2.3
Genlocked Mode.................................................................................. Error! Bookmark not defined.
5.3
P
USH
B
UTTON
B
ASED
SD/HD/3G
SDI
E
VALUATION
..................................................................................... 19
5.3.1
Push Button Main Menu .................................................................................................................... 19
5.3.2
System Mode ..................................................................................................................................... 20
5.3.3
Datapath Menu .................................................................................................................................. 20
5.3.4
Video Format Menu ........................................................................................................................... 20
5.3.5
Frequency Menu ................................................................................................................................ 21
5.4
FPGA
R
EGISTER
M
AP
................................................................................................................................. 21
5.4.1
Miscellaneous Registers:................................................................................................................... 22
5.4.2
Reset Registers ................................................................................................................................. 22
5.4.3
Rx Video Registers ............................................................................................................................ 22
5.4.4
Datapath Registers ............................................................................................................................ 24
5.4.5
Clocking ............................................................................................................................................. 26
5.4.6
Video Timing ...................................................................................................................................... 26
5.5
S
UPPORTED
T
EST
P
ATTERNS
....................................................................................................................... 29
6
....
Documentation 30
7
....
Schematics, BOMs, and Data Sheets 30
8
....
Reference FPGA IP
30
9
....
Up to Date Information 30
10
..
Part Numbers 30
