July
2009
Rev
0.06
Page 17 of 31
4.2.2
Analog Sync TPG mode
In Analog Sync TPG mode, the user provides an analog sync signal to the analog sync input on the evaluation
board (the BNC connector labeled ‘Analog IN’). The LMH1981 extracts the sync information from this signal and
passes it to the LMH1982 which generates video clocks for the FPGA, which are then used to clock the LMH0340
serializer and provide an SDI test signal output which is genlocked to the Analog input.
Figure 14 Analog Sync TPG Mode
4.2.3
Analog Sync Reclock Mode
In Analog Sync Reclock Mode, you provide both an analog Sync input as in the Analog Sync TPG mode, and an
SDI input which is genlocked to the Analog Sync input. The timing information is extracted from the analog
signal, and a new serial clock is generated using the LMH1982, and this clock is used to reclock the data
received through the SDI input port.
4.2.4
Analog Sync alternate TPG Mode
In Analog Sync Alternate TPG Mode, the system operates in a similar manner to the Analog Sync TPG mode,
except that the output video format need not be the same as the analog sync input. For example you could use
an analog sync from an NTSC 525 line 59.94 frame rate signal, and generate an SDI output which is an HD,
720P50 output.
