July
2009
Rev
0.06
Page 6 of 31
2.1
Cyclone III Development Board (Main Board) Description
The main board has a Cyclone III FPGA. The FPGA provides the SD/HD/3G SDI and general purpose stacks as
well as the control interfaces through the supplied example firmware. The daughter board is connected to the
main board through the high speed mezzanine connector (HSMC), J8. This connector provides power, control
bus, and data bus. The main board communicates to a PC through a USB cable.
Figure 3 Cyclone III Development Board
2.2
Cyclone III Development Board Termination Resistors
The Altera Cyclone III device does not have any internal termination on the receive LVDS I/O’s. Termination
resistors must be added to the Cyclone III board. The terminations resistors must be placed as close to the
FPGA’s pin as possible. The 3C120 host board has the layout footprints for the termination resistors. Eleven 100
Ohm resistors in 0402 package size are required to install onto the host board. The resistors are located on the
bottom side of the board. They are between the FPGA and the HSMC port A connector. Figures 4 and 5 show the
schematic and board location of the LVDS termination resistors.
