Configuration and Installation Chapter 2
SCXI-1160 User Manual 2-21 © National Instruments Corporation
4. Set SLOT0SEL* to 1. This will assert the SS* line of the module whose slot number was
written to Slot 0. If multiple chassis are being used, only the appropriate slot in the chassis
whose address corresponds to the written chassis number will be selected. When no
communication is taking place between the data acquisition board and any modules, write
zero to the Slot-Select Register to ensure that no accidental writes occur.
Figure 2-9 shows the timing requirements on the SERCLK and SERDATIN signals. You must
observe these timing requirements for all communications. T
delay
is a specification of the
SCXI-1160.
Tlow
Thigh
SERCLK
SERDATIN
SERDATOUT
Tsetup
Thold
Tdelay
Tlow
Minimum low time 65 nsec minimum
Thigh
Minimum high time 400 nsec minimum
Tsetup
SERDATIN setup time
200 nsec minimum
Thold
SERDATIN hold time 200 nsec minimum
Tdelay
SERDATOUT delay 350 nsec maximum
Figure 2-9. Serial Data Timing Diagram
After selecting the module slot as previously described, you must write first to the Address
Handler, then to the register of interest for each write or read cycle to the module.
To write to the Address Handler, follow these steps:
1. Initial conditions:
SS* asserted low.
SERDATIN = don't care.
DAQD*/A = 1 (indicates data will be written to the Address Handler).
SLOT0SEL* = 1.
SERCLK = 1 (and has not transitioned since SS* went low).
2. For each bit, starting with the MSB, perform the following action:
Establish the desired SERDATIN level corresponding to this bit.
SERCLK = 0.
SERCLK = 1. This rising edge clocks the data.
These bits are the address of the register of interest.