Table 6. Clock Configuration Options
Clock Configuration
External
Clock Type
External
Clock
Frequency
Description
Internal Reference
Clock
13
—
—
The internal Sample Clock locks to
an onboard voltage-controlled
temperature compensated crystal
oscillator (VCTCXO).
Internal PXI_CLK10
—
10 MHz
The internal Sample Clock locks to
the PXI 10 MHz Reference Clock,
which is provided through the
backplane.
External Reference
Clock (CLK/REF IN)
Reference
Clock
10 MHz
14
The internal Sample Clock locks to
an external Reference Clock,
which is provided through the
CLK/REF IN front panel
connector.
External Sample
Clock (CLK/REF IN)
Sample Clock
1 GHz
15
An external Sample Clock can be
provided through the CLK/REF IN
front panel connector.
13
Default clock configuration.
14
The PLL Reference Clock must be accurate to ±25 ppm.
15
The ADC sample rate is 500 MS/s with a 1 GHz clock.
14
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PXIe-5763 Specifications
