LabVIEW FPGA DRAM clock rate
267 MHz
LabVIEW FPGA DRAM bus width
256 bit per bank
Maximum theoretical data rate
17 GB/s (8.5 GB/s per bank)
Analog Input
General Characteristics
Number of channels
4, single-ended, simultaneously sampled
Connector type
SMA
Input impedance
50 Ω
Input coupling
AC or DC
6
Sample Rate
Internal Sample Clock
500 MHz
External Sample Clock
500 MHz
7
Analog-to-digital converter (ADC)
ADS54J69, 16-bit resolution
Typical Specifications
Full-scale input range (normal operating conditions)
AC-coupled
2.03 V
pp
(10.15 dBm) at 10 MHz
DC-coupled
1.97 V
pp
(9.87 dBm)
Gain accuracy
AC-coupled
±0.1 dB at 10 MHz
DC-coupled
±1% at DC
DC Offset
AC-coupled
±41 µV
DC-coupled
±225 µV
Bandwidth (-3 dB)
8
AC-coupled
0.07 MHz to 225 MHz
DC-coupled
DC to 225 MHz
9
6
Only one analog input path type is populated.
7
You must provide a 1 GHz clock at the CLK/REF IN front panel connector to enable this rate.
8
Normalized to 10 MHz.
9
Upper -3 dB bandwidth limited by ADC decimation filter.
6
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PXIe-5763 Specifications