Chapter 3
Hardware Overview
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National Instruments Corporation
3-3
CSYNC Mux
This multiplexer routes either the video signal or an external CSYNC
signal to the genlock circuit. If this circuit routes the video signal to the
genlock circuit, then the internally generated CSYNC can be routed to
the BNC as an output signal.
Genlock SYNC Generator
This circuit generates the necessary clock and synchronization signals
to digitize the incoming video signal correctly. The genlock circuit can
produce pixel clock frequencies between 11.66 MHz and 15.78 MHz,
which accommodate RS-170 and CCIR-601 video standards.
Pixel Aspect Ratio Circuitry
The pixel aspect ratio is the ratio between the horizontal size to the vertical
size of the pixel. Use this value to adjust or correct the picture aspect ratio.
For more information, see the
section later in
this chapter.
Acquisition and Region-of-Interest Control
The acquisition and region-of-interest control circuitry monitors the
incoming video signal and routes the active pixels to the FIFO buffers.
The PCI/PXI-1407 can digitize an entire frame and perform pixel and line
scaling and region-of-interest acquisition. Pixel and line scaling lets the
PCI-1407 transfer certain multiples (2, 4, or 8) of pixels and lines to the PCI
bus. In region-of-interest acquisition, you select an area in the acquisition
window to transfer to the PCI bus.
FIFO Buffer
The PCI/PXI-1407 uses a 4 KB FIFO buffer for temporary storage of the
image being transferred to the PCI system memory or display memory.
The buffer stores six full video lines during image acquisition.
Scatter-Gather DMA Controllers
The PCI/PXI-1407 uses three independent onboard direct memory access
(DMA) controllers. The DMA controllers transfer data between the
onboard first-in first-out (FIFO) memory buffers and the PCI bus. Each of
these controllers supports scatter-gather DMA, which allows the DMA
