Index
©
National Instruments Corporation
I-5
acquisition start trigger, 3-17
delta-sigma ADCs and the oversample
relationship between sample rate and
oversample clock (table), 3-15
reset period as a function of sample rate
system integration services, B-1
T
technical support, B-1
telephone technical support, B-2
test panels for acquiring signals, 2-10
testing device configuration, 2-3
theory of operation
analog input signal connections, 3-3
ADC, 3-9
analog input stage (figure), 3-3
anti-alias filtering, 3-4
calibration, 3-4
noise, 3-4
block diagrams
analog function block diagram, 3-2
digital function block diagram, 3-1
I/O connectors, 3-2
triggers, 3-11
above-high-level triggering mode
below-low-level triggering mode
high-hysteresis triggering mode
low-hysteresis triggering mode
training
above-high-level triggering mode
below-low-level triggering mode
digital trigger, 2-10
high-hysteresis triggering mode
low-hysteresis triggering mode
specifications
analog trigger, A-7
digital trigger, A-7
troubleshooting resources, B-1
U
unpacking NI 447
X
W
Web