Chapter 5
Counters
©
National Instruments Corporation
5-3
Analog Output Series User Manual
but with the source signal inverted and referenced to the falling edge of the
source signal, applies when you program the counter to count falling edges.
The gate input timing parameters are referenced to the signal at the
source input or to one of the internally generated signals on your device.
Figure 5-2 shows the gate signal referenced to the rising edge of a source
signal. The gate must be valid (either high or low) for at least 10 ns before
the rising or falling edge of a source signal so the gate can take effect at that
source edge, as shown by t
gsu
and t
gh
. The gate signal is not required after
the active edge of the source signal.
If you use an internal timebase clock, you cannot synchronize the gate
signal with the clock. In this case, gates applied close to a source edge take
effect either on that source edge or on the next one. This arrangement
results in an uncertainty of one source clock period with respect to
unsynchronized gating sources.
The output timing parameters are referenced to the signal at the source
input or to one of the internally generated clock signals on your device.
Figure 5-2 shows the out signal referenced to the rising edge of a source
signal. Any out signal state changes occur within 80 ns after the rising or
falling edge of the source signal.
For information on the internal routing available on the DAQ-STC
counter/timers, refer to
Counter Parts in NI-DAQmx
in the
NI-DAQmx
Help
or the
LabVIEW Help
in version 8.0 for more information.
Counter 0 Source Signal
You can select any PFI as well as many other internal signals as the Counter
0 Source (Ctr0Source) signal. The Ctr0Source signal is configured in
edge-detection mode on either the rising or falling edge. The selected edge
of the Ctr0Source signal increments and decrements the counter value
depending on the application the counter is performing.
You can export the Ctr0Source signal to the PFI 8/CTR 0 SOURCE pin,
even if another PFI is inputting the Ctr0Source signal. This output is set to
high-impedance at startup.