Appendix A
Device-Specific Information
©
National Instruments Corporation
A-3
Analog Output Series User Manual
Block Diagram (NI 6711/6713)
Figure A-1 shows a block diagram of the NI 6711/6713.
Figure A-1.
NI 6711/6713 Block Diagram
Timing
PFI / Trigger
I/O Connector
RT
S
I B
us
PCI/PXI B
us
Digit
a
l I/O (8)
EEPROM
C
a
li
b
r
a
tion
M
u
x
C
a
li
b
r
a
tion
ADC
C
a
li
b
r
a
tion
DAC
s
AO 4
L
a
tch
24
8
12
AO 4
12-Bit DAC
AO 4
Amp
DAQ -
S
TC
An
a
log O
u
tp
u
t
Timing/Control
An
a
log Inp
u
t
Timing/Control
Digit
a
l I/O
Trigger
Co
u
nter/
Timing I/O
RT
S
I B
us
Interf
a
ce
DMA/IRQ
B
us
Interf
a
ce
Addre
ss
/D
a
t
a
Addre
ss
Control
EEPROM
Control
AO
Control
C
a
li
b
r
a
tion
Control
DMA/
IRQ
Regi
s
ter
Decode
FPGA
DAQ-
S
TC
B
us
Interf
a
ce
PCI
MITE
Generic
B
us
Interf
a
ce
PCI
B
us
Interf
a
ce
IRQ
DMA
AO 5
L
a
tch
12
AO 5
12-Bit DAC
AO 6
L
a
tch
12
AO 6
12-Bit DAC
AO 7
L
a
tch
12
AO 7
12-Bit DAC
DAC
FIFO
AO 5
Amp
AO 6
Amp
AO 7
Amp
D
a
t
a
D
a
t
a
D
a
t
a
AO Control
AO 0
L
a
tch
12
AO 0
12-Bit DAC
AO 0
Amp
AO 1
L
a
tch
12
AO 1
12-Bit DAC
AO 2
L
a
tch
12
AO 2
12-Bit DAC
AO
3
L
a
tch
12
AO
3
12-Bit DAC
AO 1
Amp
AO 2
Amp
AO
3
Amp
D
a
t
a
1A
+5 V
Note: AO_<4..7>
a
ppe
a
r only on the NI 671
3
.