National Instruments AT-MIO-16D, Руководство пользователя

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Configuration and Installation Chapter 2
AT-MIO-16D User Manual 2-42 © National Instruments Corporation
The GATE and OUT signal transitions in Figure 2-39 are referenced to the rising edge of the
SOURCE signal. This timing diagram assumes that the counters are programmed to count rising
edges. The same timing diagram, with the source signal inverted and referenced to the falling edge
of the source signal, applies to the case in which the counter is programmed to count falling edges.
The signal applied at a SOURCE input can be used as a clock source by any of the Am9513A
counter/timers and by the Am9513A frequency division output FOUT. The signal applied to a
SOURCE input must not exceed a frequency of 6 MHz for proper operation of the Am9513A.
The Am9513A counters can be individually programmed to count rising or falling edges of
signals applied at any of the Am9513A SOURCE or GATE input pins.
In addition to the signals applied to the SOURCE and GATE inputs, the Am9513A generates five
internal timebase clocks from the clock signal supplied by the AT-MIO-16D. This clock signal is
selected by the W5 jumper and then divided by 10. The factory default value is 1 MHz into the
Am9513A (10-MHz clock signal on the AT-MIO-16D). The five internal timebase clocks can be
used as counting sources, and these clocks have a maximum skew of 75 nsec between them. The
SOURCE signal shown in Figure 2-38 represents any of the signals applied at the SOURCE
inputs, GATE inputs, or internal timebase clocks. See Appendix E, Am9513A Data Sheet, for
further details.
Specifications for signals at the GATE input are referenced to the signal at the SOURCE input or
one of the Am9513A internally generated signals. Figure 2-39 shows the GATE signal referenced
to the rising edge of a source signal. The gate must be valid (either high or low) at least 100 nsec
before the rising or falling edge of a source signal for the gate to take effect at that source edge (as
shown by tgsu and tgh in Figure 2-39). Similarly, the gate signal must be held for at least 10 nsec
after the rising or falling edge of a source signal for the gate to take effect at that source edge. The
gate high or low period must be at least 145 nsec in duration. If an internal timebase clock is used,
the gate signal cannot be synchronized with the clock. In this case, gates applied close to a source
edge take effect either on that source edge or on the next one. This arrangement provides an
uncertainty of one source clock period with respect to unsynchronized gating sources.
Signals generated at the OUT output are referenced to the signal at the SOURCE input or to one of
the Am9513A internally generated clock signals. Figure 2-39 shows the OUT signal referenced to
the rising edge of a source signal. Any OUT signal state changes occur within 300 nsec after the
source signal rising or falling edge.