Chapter 3
Theory of Operation
© National Instruments Corporation
3-3
AT-MIO-16D User Manual
PC AT I/O Channel
PC AT I/O
Channel
Timing
Interface
Address
Latches
Data
Buffers
DMA
Control
Circuitry
Interrupt
Control
Circuitry
Address
Decoder
Register
Selects
Read & Write
Signals
Internal
Data Bus
AT-MIO-16D
DMA Request
AT-MIO-16D
DMA Acknowledge
& Terminal Count
AT-MIO-16D
Interrupt
Request
Address
I/O Channel
Control Lines
DMA Request
IRQ
Bus
16
/
Data
Bus
DMA
Acknowledge
Figure 3-2. PC AT I/O Channel Interface Circuitry Block Diagram
The PC AT I/O channel interface circuitry consists of address latches, address decoder circuitry,
data buffers, PC AT I/O channel interface timing signals, interrupt circuitry, and DMA arbitration
circuitry. The PC AT I/O channel interface circuitry generates the signals necessary to control and
monitor the operation of the AT-MIO-16D multiple function circuitry.
The PC AT I/O channel has 24 address lines; the AT-MIO-16D uses 10 of these lines to decode the
board address. Therefore, the board address range is hex 000 to 3FF. SA5 through SA9 are used
to generate the board enable signal. SA0 through SA4 are used to select onboard registers. These
address lines are latched by the address latches at the beginning of an I/O transfer. The latched
address lines send the same address to the address-decoding circuitry during the entire I/O transfer
cycle. The address-decoding circuitry generates the register select signals that specify which
AT-MIO-16D register is being accessed. The data buffers control the direction of data transfer on
the bidirectional data lines based on whether the transfer is a read or a write.
The PC AT I/O channel interface timing signals are used to generate read-and-write signals and to
define the transfer cycle. A transfer cycle can be either an 8-bit or a 16-bit data I/O operation. The
AT-MIO-16D returns signals to the PC AT I/O channel to indicate when the board has been
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