National Instruments AT-MIO-16D, Руководство пользователя

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Chapter 3 Theory of Operation
© National Instruments Corporation 3-7 AT-MIO-16D User Manual
it is performing an A/D conversion. Without the sample-and-hold amplifier, the analog input
signal could change during a conversion, thereby causing errors during A/D conversion. By
isolating the ADC from the analog input signals during conversion, you can change the input
multiplexer and allow the instrumentation amplifier to settle to a new value while the ADC is
converting the old value. This isolation creates a two-stage pipeline and increases and optimizes
the performance of the analog input circuitry during high-speed, multiple A/D conversions.
A/D Converter
The ADC is a 12-bit, successive-approximation ADC with a maximum conversion time of 9
m
sec.
The 12-bit resolution allows the converter to resolve its input range into 4,096 different steps.
This resolution also provides a 12-bit digital word that represents the value of the input voltage
level with respect to the converter input range. The ADC supports three input ranges that are
jumper-selectable on the AT-MIO-16D board, -10ÊtoÊ+10 V, -5 to +5 V, or 0 to +10 V.
ADC FIFO Buffer
When an A/D conversion is complete, the ADC clocks the result into the A/D FIFO. The A/D
FIFO is 12 bits wide and 512 words deep. This FIFO serves as a buffer to the ADC and provides
two benefits. Any time an A/D conversion is complete, the value is saved in the A/D FIFO for later
reading, and the ADC is free to start a new conversion. Secondly, the A/D FIFO can collect up to
512 A/D conversion values before any information is lost; thus software or DMA has extra time
(512 times the sample interval) to catch up with the hardware. If more than 512 values are stored
in the A/D FIFO without the A/D FIFO being read from, an error condition called A/D FIFO
overflow occurs and A/D conversion information is lost.
The A/D FIFO generates a signal that indicates when it contains A/D conversion data. You can
read the state of this signal from the AT-MIO-16D Status Register. You can use this signal to
generate a DMA request signal or to generate an interrupt. Sign-extension circuitry at the A/D
FIFO output adds four most significant bits (MSBs), bits 15 through 12, to the 12-bit FIFO output
(bits 11 through 0) to produce a 16-bit result.
The sign-extension circuitry is software programmable to generate either straight binary numbers
or two's complement numbers. In straight binary mode, bits 15 through 12 are always zero and
provide a range of 0 to 4,095. In two's complement mode, the MSB of the 12-bit ADC result, bit
11, is inverted and extended to bits 15 through 12, providing a range of -2,048 to +2,047.
Data Acquisition Timing Circuitry
A data acquisition operation refers to the process of taking a sequence of A/D conversions with the
sample interval (the time between successive A/D conversions) carefully timed. The data
acquisition timing circuitry consists of various clocks and timing signals. Three types of data
acquisition are supported by the AT-MIO-16D boardÐsingle-channel data acquisition, multiple-
channel data acquisition with continuous scanning, and multiple-channel data acquisition with
interval scanning.
Scanned data acquisition uses the multiplexer counter and the mux-gain memory to automatically
switch between analog input channels during data acquisition. Continuous scanning cycles
through the mux-gain memory without any delays between cycles. Interval scanning assigns a