Chapter 5
Theory of Operation and Register-Level Programming
©
National Instruments Corporation
5-9
Figure 5-5.
Scanning Order for Different AMUX-64T Board Configurations
Scanning Order
Single Board Configuration
CH0
CH1
CH2
CH3
Board A
0
1
2
3
CH0, MIO Board
Two Board Configuration
Board B
4
5
6
7
CH0
CH1
CH2
CH3
Board A
Scanning Order
0
1
2
3
CH0, MIO Board
CH0 (64)
CH1 (65)
CH2 (66)
CH3 (67)
8
9
10
11
CH0
CH1
CH2
CH3
Board A
Four Board Configuration
Scanning Order
0
1
2
3
CH0, MIO Board
Board B
4
5
6
7
Board C
Board D
12
13
14
15
Channel Number as Labeled on AMUX-64T
Channel Number as Addressed from MIO Board
CH0 (64)
CH1 (65)
CH2 (66)
CH3 (67)
CH0 (128)
CH1 (129)
CH2 (130)
CH3 (131)
CH0 (192)
CH1 (193)
CH2 (194)
CH3 (195)