Chapter 3
Hardware Overview
6711/6713/6715 User Manual
3-2
www.ni.com
Figure 3-1.
6711/6713 Block Diagram
400
Mbps
1394 PHY
DAQPad-6713 only
Timing
PFI / Trigger
I/O Connector
RTSI Bus
PCI/PXI
IEEE 1394
Digital I/O (8)
EEPROM
Calibration
Mux
Calibration
ADC
Calibration
DACs
CH4
Latch
24
8
12
CH4
12-Bit DAC
CH4
Amp
DAQ - STC
Analog Output
Timing/Control
Analog Input
Timing/Control
Digital I/O
Trigger
Counter/
Timing I/O
RTSI Bus
Interface
DMA/IRQ
Bus
Interface
Address/Data
Address/Data
Address
Control
EEPROM
Control
AO
Control
Calibration
Control
DMA/
IRQ
Register
Decode
FPGA
DAQ-STC
Bus
Interface
PCI
MITE
Generic
Bus
Interface
PCI
Bus
Interface
IRQ
DMA
CH5
Latch
12
CH5
12-Bit DAC
CH6
Latch
12
CH6
12-Bit DAC
CH7
Latch
12
CH7
12-Bit DAC
DAC
FIFO
NI
Firephli
CH5
Amp
CH6
Amp
CH7
Amp
Data
Data
Data
AO Control
CH0
Latch
12
CH0
12-Bit DAC
CH0
Amp
CH1
Latch
12
CH1
12-Bit DAC
CH2
Latch
12
CH2
12-Bit DAC
CH3
Latch
12
CH3
12-Bit DAC
CH1
Amp
CH2
Amp
CH3
Amp
Data
1A
+5 V
Note: CH4 through CH7 on 6713 only
Control
Control
Data
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