Motorola PPC/PMC-8260/DS1, Справочное руководство, Страница: 138 / 150

Synchronizing the Clock TDM Channel Configuration
6 - 6 PPC/PMC-8260/DS1
Configuring the PPC/PMC-8260/DS1 as Clock Slave
Depending on which clock line (A or B) is the H.110 bus master clock line, pro-
gram CT_C8_A or CT_C8_B and CT_FRAME_A or CT_FRAME_B inside the
T8105 as input. The clocks are then distributed via frame pulse clock line L_SC_1
and bit clock line TCLK_OUT and a clock driver to the clock lines of the framers
(BTCLK, BTFP) and the PowerQUICC II (L1RCLK and L1RSYNC). Figure 17
“Local TDM Clocking Structure” on page 6-5 shows these clock lines.
The T8105 general purpose I/O pins FET_CTRL_A and FET_CTRL_B must be
configured to activate the 33 Ohm series resistors of line A and B. This is accom-
plished by setting the bits FET_CTRL_A and FET_CTRL_B to 1 (default).
For information on the T8105 and the registers needed for programming, refer to
the T8105 data sheets.