Motorola M5271EVB, Руководство пользователя

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1-20 M5271EVB User’s Manual
Connectors and User Components
1.5.2 Reset Switch (SW3)
The reset logic provides system initilization. Reset occurs during power-on or via assertion
of the signal RESET which causes the MCF5271 to perform a hardare reset. Reset is also
triggered by the reset switch (SW3) which resets the entire processor/system.
A hard reset and voltage sense controller (U17) is used to produce an active low power-on
RESET signal. The reset switch SW3 is fed into U17 which generates the signal which is
fed to the MCF5271 reset, RESET. The RESET signal is an open collector signal and so
can be wire OR’ed with other reset signals from additional peripherals. On the EVB,
RESET is wire OR’d with the BDM reset signal and there is a reset signal brought out to
the expansion connectors for use with user hardware.
17 D3 18 OE
19 D0 20 DTOUT1
21 DTIN1 22 +3.3V
23 +3.3V 24 IRQ6
25 IRQ7 26 TSIZ0
27 TSIZ1 28 IRQ2
29 IRQ3 30 IRQ4
31 IRQ5 32 TCLK/PSTCLK
33 DTOUT2 34 DTIN2
35 IRQ1 36 TDI/DSI
37 TDO/DSO 38 TMS/BKPT
39 TRST/DSCLK 40 GND
41 GND 42 PST3
43 PST1 44 PST2
45 PST0 46 DDATA0
47 DDATA2 48 DDATA1
49 GND 50 GND
51 JTAG_EN 52 RCON
53 GND 54 RSTOUT
55 GND 56 RESET
57 GND 58 GND
59 GND 60 GND
Pin Signal Pin Signal