Motorola M5271EVB, Руководство пользователя

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5 5
4 4
3 3
2 2
1 1
D
D
C
C
B
B
A
A
/IRQ7
/IRQ[7:1]
D16 D20
D[31:0]
D19 D25 D24 D21
CLKMOD[1:0]
CLKMOD1 CLKMOD0
/IRQ2
/CS6 /CS5
/IRQ7
/CS7
/IRQ6
/IRQ[7:1]
/CS4
/IRQ5
/CS3
/IRQ3 /IRQ1
/CS2
/IRQ4
/CS0
/CS[7:0]
/CS0 /CS1
/BS[3:0]
/BS0 /BS1 /BS2 /BS3
/RESET
/BDM_RSTIN /EXT_RSTIN
ETH_CLK
XTAL
/IRQ[7:1]
JTAG_EN
/RSTOUT
D[31:0]
/RCON
CLKMOD[1:0]
/RSTOUT
/CS[7:0]
R/W
/BS[3:0]
TDI/DSI
/OE
TDO/DSO
/IRQ[7:1]
/TA
TRST/DSCLK
TSIZ0
TMS/BKPT
TSIZ1
CLKOUT
/TS
/TA
/CS[7:0]
R/W
/OE
/TEA /TIP
/TS
EXTAL
DTOUT2 DTOUT3 DTOUT1 DTOUT0
DTIN2 DTIN1 DTIN0 DTIN3
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V +3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V +3.3V
+3.3V
+3.3V
+3.3V
VSSPLL
VSSPLL
VSSPLL
+3.3V
Title Size
Document Number
Rev
D
a
te
:
Sheet
of
Reset Configuration & Clock selection
1
.3
M5271EVB
C
11
13
Wednesday, April 21, 2004
Title Size
Document Number
Rev
D
a
te
:
Sheet
of
Reset Configuration & Clock selection
1
.3
M5271EVB
C
11
13
Wednesday, April 21, 2004
Title Size
Document Number
Rev
D
a
te
:
Sheet
of
Reset Configuration & Clock selection
1
.3
M5271EVB
C
11
13
Wednesday, April 21, 2004
ABORT/-INT7
DEBOUNCED /IRQ7 SIGNAL HARD RESET & VOLTAGE SENSE CONTROLLER
Buffered and "OR'd" /RSTI signal to the CPU from the BDM port, expansion connectors or reset switch.
NOTE: signal track lengths between these clock circuits and the MCF5271 should be minimised.
OSCILLATOR - dual layout footprint for 8 AND 14 pin socketed DIL osc.'s
D24 D21 D20 D19 D16 CLKMOD0 CLKMOD1 JTAG_EN RCON
IMPORTANT NOTE: THE /RSTOUT SIGNAL MUST BE USED TO DRIVE THE OUTPUT ENABLE PINS OF U19 TO ALLOW THE D16, D17, D18, D19, D21, D24, D25 & D26 SIGNALS TO BE LATCHED CORRECTLY BY THE MCF5270/1 FOR CONFIGURATION AT RESET.
Closed/On
Open/Off
D25
Encoded Address/Chip Select Mode SW4-9 SW4-10 Mode ----------- ----------- -------------------------- OFF OFF PF[7:5] = /CS[6:4] OFF ON PF7 = /CS6, PF[6:5] = A[22:21] ON OFF PF[7:6] = /CS[6:5], PF[5] = A21 ON ON PF[7:5] = A[23:21]
NOTE: Please place these tables on the silkscreen on the topside of the PCB close to SW4.
Encoded Boot Device (Port Size) SW4-6 SW4-7 Mode ----------- ----------- -------------------------- OFF OFF External (32-bit) OFF ON External (16-bit) ON OFF External (8-bit) ON ON External (32-bit)
Encoded Operating Mode SW4-5 Mode ----------- ----------- OFF Reserved O
N
M
a
s
te
r
Encoded Clock Mode SW4-3 SW4-4 Mode ----------- ----------- -------------------------------------------------- OFF OFF External Clock - (No PLL) OFF ON 1:1 PLL ON OFF Normal PLL operation (Ext. Clock) ON ON Normal PLL operation (Ext. Crystal)
------------------------ OFF - SW4 - ON ------------------------ Chip Config. Off 1 Chip Config. On JTAG Interface Enabled 2 BDM Interface Enabled Encoded Clock Mode 3 Encoded Clock Mode Encoded Clock Mode 4 Encoded Clock Mode Encoded Oper. Mode 5 Encoded Oper. Mode Encoded Boot Device 6 Encoded Boot Device Encoded Boot Device 7 Encoded Boot Device Partial Bus Drive 8 Full Bus Drive Encoded Address Mode 9 Encoded Address Mode Encoded Address Mode 10 Encoded Address Mode
Note: default setting for SW4 is all switches closed/on.
Important Note - all unconnected pull-up and pull-down resistor pack connections, on all schematics pages, need to be connected to an unmasked via. NOTE: Place TP8, TP9, TP10 & TP11 at the corners of the PCB to allow easy connection of 'scope probe ground leads.
NOTE: Please place D17 through D24 together in a line.
DTIN0 LED DTIN1 LED DTIN2 LED DTIN3 LED
DTOUT0 LED DTOUT1 LED DTOUT2 LED DTOUT3 LED
Crystal Enable
Default setting for JP13 through JP20 is fitted.
External Clock Input (SMA connector)
Place TP5 as close to EXTAL as possible
Motorola SPS TSPG - TECD ColdFire Group
Default setting for JP10 is between pins 1 & 2.
Default setting for JP11 is between pins 1 & 2.
Default setting for JP12 is fitted.
OE1
1
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
GND
10
O7
11
O6
12
O5
13
O4
14
O3
15
O2
16
O1
17
O0
18
OE2
19
VCC
20
U19
MC74LCX541DT
U19
MC74LCX541DT
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP10 4x 4.7K RP10 4x 4.7K
1
TP10
GROUND
TP10
GROUND
SW3
KS11R23CQD
RESET
SW3
KS11R23CQD
RESET
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP11 4x 4.7K RP11 4x 4.7K
OE
1
GND
7
CLK
8
VDD
14
OE
4
VDD
11
U15
25MHz
U15
25MHz
1
TP9
GROUND
TP9
GROUND
R27 270 R27 270
1
2
JP15JP15
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP12 4x 4.7K RP12 4x 4.7K
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP13
4x 10K
RP13
4x 10K
1
2
3
JP10JP10
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP20
4x 4.7K
RP20
4x 4.7K
D24D24
SW2
KS11R22CQD
SW2
KS11R22CQD
MR
1
VCC
2
GND
3
PFI
4
PFO
5
N.C.
6
RESET
7
RESET
8
U17 ADM708SAR U17 ADM708SAR
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP16 4x 4.7K RP16 4x 4.7K
MR
1
VCC
2
GND
3
PFI
4
PFO
5
N.C.
6
RESET
7
RESET
8
U16 ADM708SAR U16 ADM708SAR
1
TP8
GROUND
TP8
GROUND
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP15 4x 4.7K RP15 4x 4.7K
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP9 4x 4.7K RP9 4x 4.7K
1
2
3
4
5
J7J7
SW4
Configuration DIP switch - Grayhill 78RB12
SW4
Configuration DIP switch - Grayhill 78RB12
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP14 4x 4.7K RP14 4x 4.7K
D20D20
D21D21
1
2
JP19JP19
D
1
5
RED -INT7 LED
D
1
5
RED -INT7 LED
R24 270 R24 270
1
2
JP13JP13
A GND B
C
VCC
Y
U18
SN74LVC1G11
U18
SN74LVC1G11
D17D17
R26
1
0
0
R26
1
0
0
R29 1K R29 1K
R25 10K R25 10K
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP19
4x 10
RP19
4x 10
Y1
25MHz
Y1
25MHz
C99 10pF C99 10pF
1
2
JP14JP14
1
2
JP17JP17
1
TP4
CHIP SELECT 0
TP4
CHIP SELECT 0
1
2
JP16JP16
1
2
JP18JP18
1
TP6
TRANSFER ACKNOWLEDGE
TP6
TRANSFER ACKNOWLEDGE
C98 10pF C98 10pF
1
2
JP20JP20
D22D22
1
TP2
OUTPUT ENABLE
TP2
OUTPUT ENABLE
1
TP11
GROUND
TP11
GROUND
D23D23
1
TP1
TRANSFER START
TP1
TRANSFER START
1
2
3
JP11JP11
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP21
4x 4.7K
RP21
4x 4.7K
1
TP3
READ NOT WRITE
TP3
READ NOT WRITE
D16
RED RESET LED
D16
RED RESET LED
R28
1
0
0
R28
1
0
0
1 2
JP12JP12
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP8 4x 4.7K RP8 4x 4.7K
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP22
4x 4.7K
RP22
4x 4.7K
1
TP5
CPU CLOCK I/P
TP5
CPU CLOCK I/P
D18D18
D19D19
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP17 4x 4.7K RP17 4x 4.7K
1
TP7
CPU CLOCK O/P
TP7
CPU CLOCK O/P
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
RP18
4x 10
RP18
4x 10