Motorola M5271EVB, Руководство пользователя

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1-12 M5271EVB User’s Manual
Support Logic
• DMA module
• QSPI module
• FEC module
• PIT
• Security module
All external interrupt inputs are edge sensitive. The active level is programmable. An
interrupt request must be held valid until an IACK cycle starts to guarantee correct
processing. Each interrupt input can have it’s priority programmed by setting the xIPL[2:0]
bits in the Interrupt Control Registers.
No interrupt sources should have the same level and priority as another. Programming two
interrupt sources with the same level and priority can result in undefined operation.
The M5271EVB hardware uses IRQ7 to support the ABORT function using the ABORT
switch (SW2). This switch is used to force an interrupt (level 7, priority 3) if the user's
program execution should be aborted without issuing a RESET (refer to Chapter 2 for more
information on ABORT). Since the ABORT switch is not capable of generating a vector in
response to a level seven interrupt acknowledge from the processor, the dBUG programs
this interrupt request for autovector mode.
Refer to MCF5271 User’s Manual for more information about the interrupt controller.
1.3.5 TA Generation
The processor starts a bus cycle by asserting CSx with the other control signals. The
processor then waits for a transfer acknowledgment (TA) either from within (Auto
acknowledge - AA mode) or from the externally addressed device before it can complete
the bus cycle. -TA is used to indicate the completion of the bus cycle. It also allows devices
with different access times to communicate with the processor properly asynchronously.
The MCF5271 processor, as part of the chip-select logic, has a built-in mechanism to
generate TA for all external devices which do not have the capability to generate this signal.
For example the Flash ROM cannot generate a TA signal. The chip-select logic is
programmed by the dBUG ROM Monitor to generate TA internally after a pre-programmed
number of wait states. In order to support future expansion of the M5271EVB, the TA input
of the processor is also connected to the Processor Expansion Bus. This allows any
expansion boards to assert this line to provide a TA signal to the processor. On the
expansion boards this signal should be generated through an open collector buffer with no
pull-up resistor; a pull-up resistor is included on this board. All TA signals from expansion
boards should be connected to this line.