MMC2001
EXTERNAL INTERFACE MODULE
MOTOROLA
REFERENCE MANUAL
7-7
7.5.6 Show Cycles
The CPU can perform data transfers to or from internal modules without using the
external bus. For debugging purposes, however, it may be desirable to have the inter-
nal address and data bus appear on the external bus. These external bus cycles,
called show cycles, are enabled by the SHEN bits in the EIM configuration register.
When show cycles are enabled, the EIM drives the internal address bus ADDR[19:0]
onto the external address bus pins ADDR[19:0]. In addition, the internal data bus sig-
nals DATA[31:16] or DATA[15:0] are driven onto the external data bus pins DATA[15:0]
according to the HDB bit in the EIM configuration register.
7.6 EIM Programming Model
Table 7-3 lists the registers in the EIM.
7.6.1 Chip-Select Control Registers
Each of the external chip selects has an enable bit as well as other control attributes.
The layout of the control register is slightly different for the CS0 output, which does
not support the programmable output function. For CS1–CS3 control registers, bits
two to 15 (i.e., bits other than the PA and CSEN bits) are undefined at reset.
Access these registers with 32-bit loads and stores only.
Figure 7-3 CS0 Control Register
Table 7-3 EIM Memory Map
Address
Use
Access
10004000
CS0 Control Register (CS0CR)
Supervisor Only
10004004
CS1 Control Register (CS1CR)
Supervisor Only
10004008
CS2 Control Register (CS2CR)
Supervisor Only
1000400C
CS3 Control Register (CS3CR)
Supervisor Only
10004010
to
10004014
Reserved
Supervisor Only
10004018
EIM Configuration Register (EIMCR)
Supervisor Only
10004020
to
10004FFF
Reserved
Supervisor Only
CS0CR — CS0 Control Register
10004000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
RESET:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
WSC
WWS
EDC
CSA
OEA
WEN
EBC
DSZ
SP
WP
0
CSEN
W
RESET:
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
Freescale Semiconductor,
I
Freescale Semiconductor, Inc.
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