INDEX
MOTOROLA
INDEX - 1
—A—
A Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Aborted Instructions . . . . . . . . . . . . . . . . . . . . 7-25
ABS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-22
Absolute Address . . . . . . . . . . . . . . . . . . . . . . 6-14
Absolute Short . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Accumulator Shifter . . . . . . . . . . . . . . . . . . . . . 3-9
Accumulators, A and B . . . . . . . . . . . . . . . . . . . 3-7
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-24
ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-26
ADDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-28
ADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-30
Address ALU . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Address Bus Signals (A0-A15) . . . . . . . . . 8-3, 8-5
Address Buses . . . . . . . . . . . . . . . . . . . . . 2-3, 2-4
Address Generation Unit (see AGU) . . . . . . . . 4-3
Address Modifier Arithmetic Types . . . . . . . . . 4-14
linear modifier . . . . . . . . . . . . . . . . . . . . . 4-16
modulo modifier . . . . . . . . . . . . . . . . . . . . 4-18
reverse-carry modifier . . . . . . . . . . . . . . . 4-22
summary . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
Address Operands . . . . . . . . . . . . . . . . . . . . . 6-10
table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
Address Register Files . . . . . . . . . . . . . . . . . . . 4-7
R, N, and M register restrictions . . . . . . A-310
Addressing Modes . . . . . . . . . 4-3, 4-8, 6-12, A-10
address register direct . . . . . . . . . . . . . . . 6-13
address register indirect . . . . . . . . . . . . . . 4-9
operators table . . . . . . . . . . . . . . . . . . . . . A-8
register direct . . . . . . . . . . . . . . . . . . . . . 6-13
special . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
timing summary . . . . . . . . . . . . . . . . . . . A-304
AGU
address ALU . . . . . . . . . . . . . . . . . . . . . . . 4-5
address output multiplexers . . . . . . . . . . . 4-6
address register . . . . . . . . . . . . . . . . . 4-3, 4-7
address register restrictions . . . . . . . . . . 7-10
architecture . . . . . . . . . . . . . . . . . . . . . . . . 4-3
modifier register . . . . . . . . . . . . . . . . . 4-5, 4-8
modifier register restrictions . . . . . . . . . . 7-10
offset register . . . . . . . . . . . . . . . . . . . 4-4, 4-7
offset register restrictions . . . . . . . . . . . . 7-10
register restrictions . . . . . . . . . . . . . . . . . 7-10
registers . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
registers operands table . . . . . . . . . . . . . . A-5
AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-32
ANDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-34
Application Development System . . . . . . . . . . 11-6
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Arithmetic Instructions . . . . . . . . . . . . . . . . . . .6-22
ASL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-36
ASR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-38
Assembler/Simulator . . . . . . . . . . . . . . . . . . . .11-4
Assistance . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16
—B—
B Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
BCHG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-40
BCLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-48
Benchmark Programs . . . . . . . . . . . . . . . . . . . B-3
Binary Operators . . . . . . . . . . . . . . . . . . . . . . . A-7
Bit Manipulation Instructions . . . . . . . . . . . . . .6-24
Bit Reverse . . . . . . . . . . . . . . . . . . . . . . . . . . .4-22
Bit Weighing . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
BSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-56
BTST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-64
Bus Control Signals . . . . . . . . . . . . . . . . . . 8-3, 8-5
Buses
address . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
transfers between . . . . . . . . . . . . . . . . . . . 2-5
Byte, length of . . . . . . . . . . . . . . . . . . . . . . . . . .6-5
—C—
Carry Bit . . . . . . . . . . . . . . . . . . . . . . . . 5-10, A-18
C-Compiler Features . . . . . . . . . . . . . . . . . . . .11-5
CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9
CKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10
considerations . . . . . . . . . . . . . . . . . . . . . 9-13
synch with EXTAL . . . . . . . . . . . . . . . . . . 9-14
CKP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10
CLGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10
Clock Stabilization Delay . . . . . . . . . . . . . . . . .7-38
CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-70
CLVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10
CMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-72
CMPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-74
Condition Code Computations (table) . . . . . . A-19
Condition Code Register (CCR) . . . . . . . 5-9, A-15
carry (bit 0) . . . . . . . . . . . . . . . . . . 5-10, A-18
extension (bit 5) . . . . . . . . . . . . . . . 5-11, A-16
limit (bit 6) . . . . . . . . . . . . . . . . . . . 5-11, A-16
negative (bit 3) . . . . . . . . . . . . . . . . 5-10, A-17
overflow (bit 1) . . . . . . . . . . . . . . . . 5-10, A-17
scaling (bit 7) . . . . . . . . . . . . . . . . . 5-11, A-16
symbols table . . . . . . . . . . . . . . . . . . . . . . . A-8
unnormalized (bit 4) . . . . . . . . . . . . 5-10, A-17
Содержание DSP56K
Страница 12: ...xii LIST of TABLES MOTOROLA List of Tables Continued Table Page Number Title Number ...
Страница 13: ...MOTOROLA DSP56K FAMILY INTRODUCTION 1 1 SECTION 1 DSP56K FAMILY INTRODUCTION ...
Страница 25: ...MOTOROLA DSP56K CENTRAL ARCHITECTURE OVERVIEW 2 1 SECTION 2 DSP56K CENTRAL ARCHITECTURE OVERVIEW ...
Страница 31: ...MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 1 SECTION 3 DATA ARITHMETIC LOGIC UNIT ...
Страница 50: ...DATA ALU SUMMARY 3 20 DATA ARITHMETIC LOGIC UNIT MOTOROLA ...
Страница 51: ...MOTOROLA ADDRESS GENERATION UNIT 4 1 SECTION 4 ADDRESS GENERATION UNIT ...
Страница 77: ...MOTOROLA PROGRAM CONTROL UNIT 5 1 SECTION 5 PROGRAM CONTROL UNIT ...
Страница 124: ...INSTRUCTION GROUPS 6 30 INSTRUCTION SET INTRODUCTION MOTOROLA ...
Страница 125: ...MOTOROLA PROCESSING STATES 7 1 SECTION 7 PROCESSING STATES STOP WAIT EXCEPTION NORMAL RESET ...
Страница 167: ...STOP PROCESSING STATE MOTOROLA PROCESSING STATES 7 43 ...
Страница 168: ...STOP PROCESSING STATE 7 44 PROCESSING STATES MOTOROLA ...
Страница 169: ...MOTOROLA PORT A 8 1 SECTION 8 PORT A ...
Страница 176: ...PORT A INTERFACE 8 8 PORT A MOTOROLA ...
Страница 177: ...MOTOROLA PLL CLOCK OSCILLATOR 9 1 SECTION 9 PLL CLOCK OSCILLATOR x x d Φ VCO ...
Страница 191: ...10 2 ON CHIP EMULATION OnCE MOTOROLA SECTION 10 ON CHIP EMULATION OnCE ...
Страница 218: ...USING THE OnCE MOTOROLA ON CHIP EMULATION OnCE 10 29 ...
Страница 604: ...INSTRUCTION ENCODING A 338 INSTRUCTION SET DETAILS MOTOROLA ...
Страница 605: ...MOTOROLA BENCHMARK PROGRAMS B 1 APPENDIX B BENCHMARK PROGRAMS T T T T T P1 P3 P2 P4 T T T ...
Страница 606: ...SECTION CONTENTS B 2 BENCHMARK PROGRAMS MOTOROLA SECTION B 1 INTRODUCTION 3 SECTION B 2 BENCHMARK PROGRAMS 3 ...
Страница 609: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 5 ...
Страница 611: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 7 ...
Страница 613: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 9 ...
Страница 615: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 11 ...