15
Timer Compare Force Register
This is a special register that allows the programmer to cause an output compare to
trigger. Writing to bit n in this register causes the action which is programmed
for output compare n to occur immediately. This is the same as if a successful
comparison had just taken place with the TCn register.
_H12CFORC:
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
FOC7
FOC6
FOC5
FOC4
FOC3
FOC2
FOC1
FOC0
Input Capture
The operation of the input capture is similar to that of the output compare. The
first step is to set up the appropriate Port T bits as input capture pins using
_H12TIOS.
Having done that, it is then necessary to select how the input capture will be
triggered. This is done using _H12TCTL3 and _H12TCTL4. Each channel has two
control bits EDGxB and EDGxA, which determine which edge triggers the input
capture. The different configurations of these bits are in Table 5.
Table 5: Input Capture selects
EDGxB EDGxA
Configuration__________
0
0
Capture disabled
0
1
Capture on rising edge
1
0
Capture on falling edge
1
1
Capture on any edge.
_H12TCTL3:
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
_H12TCTL4:
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
Just as with the output compare operation, the timer interrupts must be disabled
and the timer module must be enabled. The values that are read in by the input
capture are stored in the appropriate _H12TCx register.
Sample Code
This code captures the time of _H12TCNT when a switch is pressed by the user.
_H12TMSK1=0x00;
// turn off interrupts
_H12TIOS=0x00;
// Set up Port T for input capture
_H12TCTL3=0x5A;
// IC7, IC6 rising edge, IC5, IC4 falling edge
_H12TCTL4=0x5F;
// IC3, IC2 rising edge, IC1, IC0 any edge
_H12TSCR=0x80;
// turn on the timer
