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13
Writable
identification
bit
write
This bit is 1 when the CAN buffer is not full,
otherwise it is 0.
25:14
Number of
writable bytes
write_bytes
Number of serial bytes that the master can
write to TD5(3)USPCAN.
31:26
Reserved bit
reserved
Reserved.
If the status[] array is defined as an 8-bit integer, and the data sequentially read out through SPI reading
status are status[0], status[1], status[2] and status[3], its data structure is shown in Figure 3.7.
Figure 3.7 Status byte data structure
After obtaining these four bytes, the user should separate the corresponding bits and use them as the
judgment benchmark for subsequent processing. Example code is as follows:
read = status[0] & 0x01;
// Separate out the readable identifier bits
read_bytes = ((status[0] & 0xFE) >> 1) + ((status[1] & 0x1F) << 7);// Separate out the number
readable bytes
write = (status[1] & (1 << 5)) ? 1 : 0;
// Separate out the writable identifier bits
write_bytes = ((status[1] & 0xC0) >> 6) + ((status[2] & 0xFF) << 2) +((status[3] & 0x03) << 10);
// Separate out the number readable bytes
In actual use, the data in the CAN send buffer of TD5(3)USPCAN will be sent out quickly, so the
write_bytes will generally return to the maximum value.
When the master does not need to read or write TD5(3)USPCAN, the control state should be switched to
the idle state. After the state is switched through the host CTL0 and CTL1 pins, it must take at least 50us to
enable TD5(3)USPCAN to read and write. Especially, after writing, it is necessary to keep the writing state for
at least 5us to ensure that the data CAN be correctly converted to CAN bus. Figure 3.8.
